Using FPGAs to accelerate verification of your next ASIC: Introducing the FPGA Co-emulator

Most ASIC IP and SoC platforms will be validated at some point using FPGAs; this task is typically known as ASIC FPGA prototyping. Such a prototype is the closest representation of the final silicon and typically used to validate and test software and perform at-speed testing of real world interfaces. At the same time, FPGAs are increasingly being used for verification due to the performance and scalability of such systems.
Alex Grove, Product Specialist at FirstEDA, introduced the FPGA Co-emulator and discussed the below two typical use cases:

  • The verification of hardware dependent software (HdS)
  • UVM simulation acceleration

You can view the Presentation Slides here

2016-02-11T06:30:40+00:0011th February, 2016|Active Event, Blog, Events|