Verification IP – Trends and Technology for FPGA and ASIC Design Verification

Adam Rose of Mentor Graphics discussed new EZ-VIP  for PCI Express that provides re-usable building blocks for common protocols and architectures for reduced test-bench assembly time for FPGA design verification at Verification Futures.

Learn more here.

2015-02-23T07:47:47+00:0023rd February, 2015|Active Event, Blog, Events|