Visit us at DVCon Europe 2014

dvcon-europe-logoT&VS will be presenting a tutorial and exhibiting at this year’s DVCon in Europe, so if you’re visiting please check out our tutorial and technical talks or come along to our stand for the latest solution demos and announcements; including asureSIGN, our leading-edge leading Requirements Driven Verification tool – or simply stop by for a chat.

The Design and Verification Conference & Exhibition Europe is a new conference for the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits, more details below.

Read the blog article: “A European Twist to DVCon.”

 

What: DVCon Europe 2014
When: October 14-15
Where: Munich, Germany
Event Details: http://dvcon-europe.org
T&VS Stand Location: Stand #1, Strauss Foyer
T&VS Tutorial: Requirements-driven Verification Methodology for Standards Compliance

  • Tuesday, Oct 14, 11:30-13:00 [Tutorial T6, Salon Bialas]
  • Presented by: Mike Bartley and Serrie Chapman

Requirements-driven verification is based on ensuring that feature-level requirements are adequately verified by tracing such requirements through to verification tasks. It is similar to Coverage-driven Verification from the sense that it is metric-driven but differs significantly because the metrics derive from requirements rather than verification goals

Requirements-driven verification is also required for compliance with the increasing number of standards that control development of hardware for domains such as automotive (ISO26262) and avionics (DO254). The tutorial will cover what the development standards mandate and how it can be delivered through requirements-driven verification methodology and will use an automotive example (lane crossing) to cover the three main issues regarding standards compliance and how they are covered through a requirements-driven verification methodology.

T&VS Talk #1: Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVM Verification

  • Wednesday, Oct 15, 11:30-12:30 [Session T2.4: Advanced Verification]
  • Presented by: Suresh Babu (Test and Verification Solutions) and Roman Wang (AMD)
T&VS Talk #2: Requirements-Driven Verification Methodology (for Standards Compliance)

  • Wednesday, Oct 15, 16:00-17:00 [Session T7.2: Verification Management]
  • Presented by: Serrie Chapman and Mike Bartley – Test and Verification Solutions
T&VS Talk #3: A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog AMS

  • Wednesday, Oct 15, 10:00-11:00 [Session T1.2: Analog / Mixed-Signal Design and Verification]
  • Presented by: Jeganath Gandhi Rajamohan, Mike Bartley – Test and Verification Solutions

About DVCon Europe

The Design and Verification Conference & Exhibition Europe is a new conference for the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, systems designers, software developers and IP integrators the latest methodologies, techniques, applications and demonstrations on the practical use of EDA and IP languages and standards used in electronic design.

 

 

2018-02-23T11:07:05+00:00 15th August, 2014|Active Event, Events, Requirements|
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