What is the Collective Noun for 250 Verification Engineers?

Next week over 250 verification engineers will gather to discuss their verification challenges and discuss potential solutions (with another 80 online).

Verification  is now the biggest task in any new semiconductor development.  Engineers and manager face a range of challenges ranging from integrating data from a range of tools, through measuring test bench quality, how to find bugs earlier and improving vertical reuse, to resourcing projects.  We will also look at the different challenges posed in FPGA verification.  Plus the 50 challenges posed at previous conferences.  You must be facing at least one of those challenges so why not come along and see if you can find a solution?

Registration is easy and free, and includes lunch, refreshments, conference bag and proceedings.  We are in Munich, Reading and Sophia, with remote access too of course.

Why not register now or forward this to a colleague?

2015-01-19T13:47:46+00:00 14th November, 2013|Events, Hardware Verification, TVS-Bristol, TVS-France|
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