Case Study: TVS helps Pactron verify complex FPGA design

pactronPactron HJPC is a leading provider of board level solutions to the semiconductor industry. Based on a qualification of TVS’ well-proven verification capabilities, Pactron chose TVS as the partner for the verification of a complex FPGA design for a financial application.

TVS created a detailed verification plan listing out the strategy for feature list extraction, test bench specification, verification plan development and functional and code coverage. Once the plan was ratified by the customer, TVS developed a System Verilog based Bus Functional Model (BFM). In addition, the verification environment was designed to support Interrupt generator BFM with constrained enumeration support for interrupt selection.

TVS set up a team of 5 people within a week of RFP and was able to achieve the target of 100% functional coverage within just 2 months. TVS’ verification strategy helped Pactron achieve cost savings of nearly 40% on functional verification.

Ram Chandrashekar, Technical Manager at Pactron, commented, “TVS was able to put together a team of qualified verification engineers in short time frame and reused a lot of its existing verification collaterals to cut the overall development time by 30% .”

Ghuru Kumaravelu, Engineering Manager at Pactron, concluded, “We are very pleased with TVS’ services and wouldn’t think twice about recommending TVS to any of our customers.”

2014-09-24T08:31:54+00:00 21st August, 2014|Hardware Verification, Thought Leadership|
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.