Pactron HJPC is a leading provider of board level solutions to the semiconductor industry. Based on a qualification of TVS’ well-proven verification capabilities, Pactron chose TVS as the partner for the verification of a complex FPGA design for a financial application.
TVS created a detailed verification plan listing out the strategy for feature list extraction, test bench specification, verification plan development and functional and code coverage. Once the plan was ratified by the customer, TVS developed a System Verilog based Bus Functional Model (BFM). In addition, the verification environment was designed to support Interrupt generator BFM with constrained enumeration support for interrupt selection.
TVS set up a team of 5 people within a week of RFP and was able to achieve the target of 100% functional coverage within just 2 months. TVS’ verification strategy helped Pactron achieve cost savings of nearly 40% on functional verification.
Ram Chandrashekar, Technical Manager at Pactron, commented, “TVS was able to put together a team of qualified verification engineers in short time frame and reused a lot of its existing verification collaterals to cut the overall development time by 30% .”
Ghuru Kumaravelu, Engineering Manager at Pactron, concluded, “We are very pleased with TVS’ services and wouldn’t think twice about recommending TVS to any of our customers.”