Do we need an Easier UVM?

At Verification Futures, Bangalore on May 13th, John Aynsley, CTO at Doulos, will be presenting on EasierTM UVM which consists of a comprehensive set of coding guidelines for the use of UVM and an open source UVM code generation tool.

The EasierTM UVM course, developed by Doulos, the global leader for the development and delivery of market leading training solutions for SoC, FPGA and ASIC design and verification, automatically generates the boilerplate UVM code for a project according to these coding guidelines and thus helps UVM make the transition from an early adopters’ sandpit to a professional methodology. If you want to increase the ease of usage of UVM in your organization, you shouldn’t miss this presentation!

Verification Futures has a number of very interesting presentations on topics such as Prototyping, AMS Verification, Co-simulation, DV flow empowerment by UVM, Generic ABCML channel scoreboard for reuse across MOST protocols, Challenges involved in Re-Use of SV-UVM Based IP Verification Environment and Why Synthesis From SystemC? All are already lined up at Verification Futures. Plus the chance to meet leading EDA companies and to network with fellow verification professionals.

Top companies like Synopsys, Mentor Graphics, Jasper, Atrenta, Real Intent and Doulos are sponsoring the event and more than 370 verification professionals from Intel, Qualcomm, Broadcom, Texas Instruments, Nvidia, LSI, NXP, IMC, Sandisk etc. have already confirmed participation. Make sure you do not miss out on this opportunity to resolve your verification challenges.

2015-01-19T12:58:09+00:00 21st April, 2014|Hardware Verification, Thought Leadership, TVS-India|
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