The enclosed technical article is a collaboration between an expert user, Mike Bartley (Test and Verification Solutions), with a senior solution architect, Sharon Rosenberg (Cadence) to provide a complete picture of the problem statement, a solution paradigm and technology, and the user benefits and impact of applying PSS technology.
As products become more complex and market windows continue to shrink, efficiency in product development can translate directly into competitive advantage. We understand what improves efficiency in verification: abstraction and reuse; but how to achieve that?
Accellera are looking to address this through the Portable Stimulus Specification (PSS).
The reuse revolution started in design IP and has contributed hugely to design efficiency. Verification IP soon followed in the form of eVC and latterly UVC but these miss the main point: the currency of verification is stimulus (and checkers, of course). Also, verification has to deal with multiple dimensions of reuse:
- Hierarchy (block, subsystem, SoC, system)
- Platform (simulation, emulation, FPGA prototype, Silicon)
- Project (reuse from one project to the next)
- PSS tries to deal with all these through abstraction.