What are your Biggest V&V Challenges?

Verification Futures has been running since 2011 in the UK and has also run in France, Germany and India.  During that time over 30 verification managers and engineers have presented their 3 top verification challenges, resulting in close to 100 different challenges being shared with the community (see table below).

Analysing that data tells us that their biggest challenge is integrating different languages, tools and strategies.  Innovation in hardware verification has brought us a slew of verification technologies to help us verify increasingly complex designs.  However, understanding how to select the right strategy combining methods, languages and tools, and then combining the results continues to be the biggest challenge we face.

As mentioned, design complexity continues to increase with a consequent increase in verification complexity.  This is cited by 8 of the speakers making it the second biggest challenge closely followed by completeness, mixed signal and debug.  Verification managers see closing verification as a major challenge leading to potentially long tails in the project execution.  Mixed signal verification challenges have been on the increase as speakers see more analog blocks appearing in designs.

Debug continues to appear very high in the list and industry research also puts debug as taking the largest percentage of verification effort on our projects. To my amazement most debug is still performed with waveforms and “printf” (although UVM allows us to write “printf” in more sophisticated ways 🙂 )  Surely debug is ripe for a major innovation to help us all save time for our scarce verification resource.

The table below gives the summary of the hardware verification challenges presented over the past 6 years.  This year the conference includes more software testing, with tracks on both safety and security.  The challenges are coming from Qualcomm, Thales and GE Aviation and as expected there are challenges around qualifying safety-related products but also familiar ones shared between both hardware and software; namely dealing with complexity and predictable execution of verification plans.

Join Us for Verification Futures 2017

Why not join us for Verification Futures this year on 6th April 2017 to hear more about the challenges and the solutions being offered. It is free to attend and there is both physical attendance in Reading, UK or virtual attendance available.

What Are Your Biggest V&V Challenges?

Help us to discover the top challenges that the community is currently facing in performing efficient hardware and software V&V by completing a short survey.  It has just two questions and shouldn’t take more than 2 minutes to complete.  Results will be presented at VF2017.  Thank You.

Table of Challenges

Challenge Description # Challenges
Integrating Languages, Tool and Techniques 10
Complexity 8
Completeness 7
Mixed Signal 7
Debug 7
Productivity 5
Requirements Driven Verif/ISO 26262 5
Reuse 5
Resources 5
FPGA Specific 5
Scalability 4
System 4
HW/SW 3
Integration Verification 3
Power Verification 3
EDA tool Integration 3
Design for Verif 2
Demonstrating Bug Absence 2
Synthesis/Timing Constraints 2
Performance 1
Change 1
Leading Edge Technology 1
Verification Data Mgt 1
Predictability 1
Measuring Test Bench Quality 1
IO Muxing at SoC Level 1
Lack of Models for Verification 1