T&VS Extends CPU Verification Tool; asureISG

The latest release of the T&VS CPU verification tool, asureISG, packs a host of new Instruction Stream Generator features:

  • Users can provide a randomization seed input and generate an instruction assembly
  • ISG supports standard SPARCv8 ISA. Other CPU ISAs can be added and multiple CPUs can be supported
  • User can define a valid memory locations and memory ranges for memory operations like load, store, other atomic operations, etc.
  • User can provide a list of valid CPU programmable registers to use during instruction assembly generation
  • User can generate a single assembly instruction or a pre-defined group of instructions with desired source and destination operands. Each instruction configuration has its own maximum limit of occurrences.
  • User can generate a sequence of instructions with desired source and destination operands, each sequence entry governed by its own successive iteration limit value
  • Instruction resources (operands) can either be fixed or defined as a range
  • User can limit the maximum number of instructions to be generated by ISG

For additional information on asureISG please view the press release.