T&VS launches larger library of Verification IP

Test and Verification Solutions (T&VS) has announced that it has expanded its asureVIP™ library of verification IP to cover protocols in MIPI, Memories, Universal Serial IO and Communication as well as a bespoke VIP development service.

The T&VS VIP offers many advantages to the user such as access to the source code, flexible licensing agreements and protocol compliance test suites. The latter enables the engineer to more quickly demonstrate that their design complies with the standard. The tests are mapped to the protocol specification so that the user can quickly see the intention of the test. Additionally the asureVIP™ library contains traffic generators which allows the chip integrator to quickly generate traffic across the interface. Synthesisable drivers and C interfaces allow the VIP to be used in emulation using SCEMI.

The UVM compliant asureVIP™ is written in native System Verilog so that debug becomes much easier given that the user has access to the code. Mike Bartley, Chief Executive Officer, Test and Verification Solutions said, “We have been working with clients on our VIP for some time now and a lot of the VIP is proven in a number of different environments and in silicon. Research suggests that companies are expanding their use of external VIP and adoption of UVM so I expect our UVM-compliant VIP to be very popular.”

The asureVIP™ library also contains eRM compliant VIP and in addition T&VS is able to VIP on demand under flexible ownership arrangements. The T&VS agile development process also means that the VIP is delivered in a number of short “sprints” allowing the client to make an early start on their verification.

For full details of the protocols available in the asureVIP™ library then please go our VIP page.

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2017-05-12T10:20:13+00:00 16th May, 2013|Hardware Verification, VIP|
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