Codasip and T&VS Deliver Advanced RISC-V Verification Solutions

10 March 2017, BRNO, CZECH Republic – Codasip, a leading RISC-V processor IP provider, and T&VS (Test and Verification Solutions), a leading verification services provider for semiconductor IP, hardware and software, today announced a broad collaboration to accelerate the verification of products based on the Codix-Bk series of RISC-V compliant processor cores.

The partnership ensures companies can be confident selecting the precise RISC-V configuration they require. The combination of Codasip’s IP generation technology and the highly-automated T&VS validated verification flows means that even the most specific configurations can be quickly verified to the highest standards. Such a capability will be essential to fully exploit the flexible, open-source RISC-V instruction set architecture (ISA).

“I am extremely pleased to see this robust solution coming into place.”, said Rick O’Connor, Executive Director of the RISC-V Foundation. “It is further evidence of the healthy and rapid growth of the RISC-V ecosystem.”

Interest in the RISC-V ISA has grown incredibly quickly and the principal advantages for design teams are the non-proprietary nature of the ISA, the availability of implementations and infrastructure from a range of suppliers and the design freedom allowed by the RISC-V standard.  However this flexibility poses a challenge for verification. Since a wide range of function/power/performance variants are possible, there is no off-the-shelf set of RISC-V validation tests, no single verification testbench, nor even a single verification flow, to fully verify an implementation.

“For customers that are now committing to RISC-V’s verification and validation have become a top concern, and rightly so.”, said Karel Masarik, CEO, Codasip, “Codasip’s partnership with T&VS allows our customers to benefit from the outstanding capabilities of T&VS as a verification company and the RISC-V UVM environment automation capabilities intrinsic to our IP.”

RISC-V verification becomes a challenge as particular functionality/performance combination that a design requires is not available in an off-the-shelf configuration. In these circumstances someone has to produce a variant of the design (RTL + Software Development Kit (SDK)) and verify it. This is clearly a challenge for RISC-V providers, whether they are Silicon IP (SIP) companies or service organizations within large companies.

“In order to thoroughly and quickly verify a new variant of the RISC-V it is crucial to have a strategy that covers the whole RISC-V family, both at the architectural and micro-architectural levels.” said Mike Bartley, CEO, T&VS, “Working with Codasip removes the guesswork from our strategy since they are able to generate new variants of the cores very rapidly, meaning that we are prepared for just about anything.”

Learn more about RISC-V IP and Verification at Embedded World 2017.

  • Visit Codasip (Booth # 3-627)
  • Visit T&VS (Booth # 3-555)

About Codasip

Codasip delivers leading-edge processor IP technology that provides the advantages of industry standard processor IP with the ability to optimize for your unique application. Codasip’s unique model-based processor IP, and application analysis technology, makes processor customization and optimization available to any design team. As a founding member of the RISC-V foundation (riscv.org) and long term supplier of LLVM and GNU based processor solutions Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe. More information on Codasip’s products and services is available at www.codasip.com.

About T&VS

T&VS (Test and Verification Solutions Ltd) provides services and products to organisations developing complex products in the microelectronics and embedded systems industries. Such organisations use T&VS to verify their hardware and software products, employ industry best practice and manage peaks in development and testing programmes. T&VS’ embedded software testing services includes onsite/offshore testing support including assistance with safety certification and security testing. T&VS hardware verification services include onsite/offshore verification support and training in advanced verification methodologies. T&VS also offers Verification IPs and its own Verification (EDA) signoff tool.

About the RISC-V Foundation

RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem. riscv.org.

All trademarks are recognized and are the property of their respective companies

2017-03-10T09:27:25+00:00 10th March, 2017|Latest Press, Press Releases, Thought Leadership|
T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.