5th RISC-V Workshop Proceedings Now Available

The Proceedings of the 5th RISC-V Workshop, hosted at Google’s Quad campus in California in November, 2016 are now available from:

The goal of the workshop was to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe and build consensus on the future evolution of the instruction set.

Each workshop helped document the rapidly rising popularity of RISC-V and the event was covered by a number of influential journals, including:

  • EETimes’ Rick Merritt
  • lowRISC’s Alex Bradbury live blogged Day 1 and Day 2;
  • Cadence’s Paul McLellan with his Breakfast Bytes blog
  • AB Open’s Gareth Halfacree with his Community Round-Up blog.

Links to these articles can be found at:

The 6th RISC-V Workshop

The 6th RISC-V Workshop will be hosted by NVIDIA and Shanghai Jiao Yong University in Shanghai China, May 9th-10th, 2016.

T&VS RISC-V Test and Verification Services

To help you deliver successful RISC-V based designs T&VS can offer specific services that build on and extend the world-class test and verification services that we have been delivering to the semiconductor industry since 2008.  Find out more.

2016-12-13T11:16:57+00:00 13th December, 2016|RISC-V, Thought Leadership|
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