Senior Digital IP Designer, RTL – JobCode: HWDSWE_260418_09 2018-04-26T12:06:42+00:00


Job Title:

Senior Digital IP Designer, RTL

Job Code:


Job Description

  • The project scope is to develop new radio technology in Radio Base Stations.
  • The work will be carried out in cooperation with other ASIC/FPGA designers.

Competence/Experience – Mandatory:

  • Long experience from ASIC/FPGA design
  • Excellent skills in VHDL, Verilog and System Verilog
  • Good programming skills (neat, commented, maintainable code, no warnings)
  • Excellent debugging skills with complex designs
  • Proficient in writing design documentation, requirements and user guides
  • Good skills in working with UNIX and/or Linux

Competence/Experience – Optional:

  • Experience in working with analog-mix-signal ASIC/FPGA devices
  • Experience in using golden models/reference models in a test bench
  • Experience in IP and UVM verification
  • Experience from working with RTL and UPF simulations
  • ClearCase version control system experience
  • Scripting in Perl, Python, Bash or C-shell
  • Experience in agile ways of working, in particular agile scrum


  • 7+ Years


  • Sweden


  • Highly competitive to match experience and capability
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