As products become more complex and market windows continue to shrink, efficiency in product development can translate directly into competitive advantage. At T&VS we understand what improves efficiency in verification: Abstraction and Reuse; but how can these be achieved?
The reuse revolution started in design IP and has contributed hugely to design efficiency. Verification IP soon followed in the form of eVC (e Verification Components) and latterly UVC (UVM Verification Components) but to a large extent they missed their target: that the main currency of verification is stimulus (and checkers, of course).
Verification also has to deal with multiple dimensions of reuse:
- Hierarchy (block, subsystem, SoC, system)
- Platform (simulation, emulation, FPGA prototype, Silicon)
- Project (reuse from one project to the next)
These challenges led to the Accellera standards organisation looking to develop a industry standard for implementing test and stimulus that would be portable from IP to full system and across multiple target platforms. In June 2017 that standard became freely available for review by early adopters as the Portable Test and Stimulus Standard (PSS), with many of its features already being incorporated into commercial products and tools.
How Can T&VS Help?
As a leading expert in test and verification and having worked on numerous test and stimulus projects it is natural that T&VS have been closely tracking the development of PSS since its inception and have worked closely with many of the companies on the Accellera Portable Stimulus Working Group. With the growing availability of tools supporting PSS T&VS are now ideally placed to provide expert, independent advice to our clients on the use of PSS and to undertake verification projects based on the growing number of tools that support the standard.
Get in Touch
To find out more and to discover how we can help deliver your next PSS -based test and stimulus projectplease contact our verification consultants today. Alternatively contact one of local sales offices.
What is PSS?
The Portable Test and Stimulus Specification (PSS) defines a standard mechanism for the specification of verification intent and behaviors that would be reusable across a wide range of target platforms (virtual, simulation, emulation, prototype, silicon, etc.) and allow for the automation of test generation. PSS It is the result of work performed by the Accellera Portable Stimulus Working Group which was formed at the beginning of 2015. The working group is comprised of 17 leading user and EDA vendor companies.
- View the PSS Standard – Early Adopter Revision for Public Review
- Press 2015: Accellera Systems Initiative Forms Portable Stimulus Working Group
- Press 2017: PSS Early Adopter Specification Now Available for Public Review
- Join the open PSS discussions on the Accellera PSS Forum
- Who is involved in the PSS Standard Work Group: AMD, AMIQ EDA, Analog Devices, Breker Verification Systems, Cadence Design Systems, Cisco, Cypress, IBM, Intel, Mentor, A Siemens Business, National Instruments, NVIDIA, NXP Semiconductors, Qualcomm, Semifore, Synopsys and Vayavya Labs.
Implementations of PSS
A growing number of tools are available that implement the PSS standard, many of which T&VS are experienced in using, including:
- Breker: TrekSoC and TrekUVM
- Cadence: Perspec System Verifier : T&VS are an authorised delivery partner
- Mentor: Questa InFact
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control.