asureISG-instruction-stream-generator 2018-03-01T14:23:30+00:00


T&VS Instruction Stream Generator

The asureISG tool from T&VS accelerates the completion of CPU code-coverage and helps discover bugs that often go unnoticed with traditional directed testing.

The tool includes support for:

  • Event generation for mimicking complex system (e.g. sensor inputs)
  • Random generation of structures (e.g., directed graphs)
  • Developed in pure C++
  • Directly generate:
    • Directed instruction assembly
    • Constrained Random instruction assembly
    • Special scenarios to verify CPU performance and corner cases
  • Generate cases with sequences, constraints and policies
  • Generate performance monitoring instruction streams, including:
    • Various kinds of inputs, resources, resource sharing, etc.
  • Configure specialized streams for specific unit-level instruction verification

White Paper

Verifying RISC-V SOCs

In the paper “A Hierarchical and Configurable Strategy to Verify RISC-V based SOCs” (presented at DVCon USA 2018) T&VS outline a verification strategy for RISC-V based IP and SOCs using asureISG.

Download at RISC-V

T&VS Extends CPU Verification Tool

The latest release of the T&VS CPU verification tool, asureISG, packs a host of new Instruction Stream Generator features:

  • Users can provide a randomization seed input and generate an instruction assembly
  • ISG supports standard SPARCv8 ISA. Other CPU ISAs can be added and multiple CPUs can be supported
  • User can define a valid memory locations and memory ranges for memory operations like load, store, other atomic operations, etc.
  • User can provide a list of valid CPU programmable registers to use during instruction assembly generation
  • User can generate a single assembly instruction or a pre-defined group of instructions with desired source and destination operands. Each instruction configuration has its own maximum limit of occurrences.
  • User can generate a sequence of instructions with desired source and destination operands, each sequence entry governed by its own successive iteration limit value
  • Instruction resources (operands) can either be fixed or defined as a range
  • User can limit the maximum number of instructions to be generated by ISG
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