Structural Testing / DFT

Continuously shrinking process nodes have introduced new and complex on-chip variation effects creating new yield challenges. Combined with ever-increasing design complexity with multiple memories, mixed signal blocks and IPs from multiple vendors crammed into a single SoC, Design for Testability (DFT) implementation and signoff has become a major challenge. The T&VS asureDFT services suite help you overcome these challenges by establishing a DFT strategy that delivers improved DFT execution quality and reduced time-to market.


asureDFT Portfolio

yellow_square T&VS DFT Solutions
  • Services
    • Scan ( Compression/ non-compression based on structure of the device and test time requirements)
    • ATPG (stuck-at, at-speed or new faults based on the technology and strategy)
    • Memory BIST with industry standard EDA tools
    • Logic BIST
    • IEEE 1149.1, IEEE1149.6 compliance test controllers (JTAG)
    • Ensuring the design integrity on pre and post DFT by Formal Verification
    • ATE support/ Diagnosis of Structural failures
  • Training
    • DFT Strategy/Structural Testing
    • Exclusive trainings on JTAG, BSCAN, SCAN, MBIST
    • Customized contents for customer requirements
  • Off-the-shelf components
    • JTAG TAP based test controllers and verification frame works (JTAG, IEEE 1149, TAP and its customized Instructions)
    • Test suites for Verifying BSCAN
    • Generating Tester compatible vectors for Post Si validation (ATE)
    • Format conversions with ATE logs for diagnosis
  • Development of DFT methodology
  • Assessment of existing DFT methodology


  • Reduced overhead – no need to hire costly DFT resources
  • End-to-end support – from design to silicon
  • Off the shelf components – reduce DFT turnaround times
  • Training support
  • Flexible business models – ODC, Resource augmentation, Managed services, Turnkey services


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