systemc-logoSystemC addresses the need for a system design and verification language that spans hardware and software. It is a language built in standard C++ by extending the language with a set of class libraries created for design and verification. T&VS customers are applying SystemC for architectural exploration, performance modelling, functional verification, and high-level synthesis.

T&VS SystemC Expertise

T&VS has the following expertise and offers the following services:

  • Architectural Exploration and Performance Modeling
    • A leading smartphone manufacturer with a reputation for shipping some of the highest performance hardware in the industry was developing an Advanced Memory Subsystem (AMS) with enhanced memory performance for bandwidth hungry blocks. T&VS was selected to develop a performance model of the memory subsystem and for exploration of the subsystems performance features. Read the case study.
  • Verification of SystemC Designs Used in High-Level Synthesis
    • Blu Wireless develops mmWave wireless technology for advanced WiGig applications using SystemC to design their silicon IP. T&VS was selected to provide a SystemC UVM environment for verification of the SystemC IP designs. Read the case study.

SystemC UVM libraries available FREE from T&VS

T&VS has made freely available the SystemC UVM it developed as part of the Blu Wireless project. The library closely mimics UVM but gives users a license free UVM-based verification environment.

Request Your FREE SystemC UVM Libraries

  • Please enter the text above in the box to help reduce spam.
  • This field is for validation purposes and should be left unchanged.

Note that SystemC is defined by the Open SystemC Initiative (OSCI) and ratified as IEEE Std. 1666™-2011.