Feature Extraction – An Introduction 2017-01-12T16:56:13+00:00

Formal Verification Training

Target Audience

  • Design Verification Engineers and Managers
  • Design Engineers wanting to understand more about feature extraction
  • Companies trying to move to the latest verification techniques and strategies

Delivery

  • 1 day of interactive style lectures and a number of case studies
  • Use of client requirements as examples is encouraged

Prerequisites

  • None, no prior knowledge is required and will also speed up the class.
  • It would be useful if some example client requirements can be provided to TVS in advance to use as examples. This is not obligatory.

Outline Course Content

  • Putting feature extraction in context
  • Worked examples of feature extraction
  • The Verification Plan
  • Some techniques to apply during feature extraction
  • The typical life-cycle of a Verification Plan
  • Exercises on simple feature extraction
  • Feature Extraction in Context
  • Additional exercises on feature extraction

Find out more

Contact one of our training consultants today to find out more about our training courses.


Alternatively contact your local sales office

T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.