The Master and Slave AMBA APB VIP (Advanced Peripheral Bus) is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting both UVM and OVM, this APB VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.
The Master and Slave components have been interoperability tested and come with a Bus Monitor for performing all protocol checks. The monitor also performs key protocol checks and reports errors for non compliance with APB 4.0 / 3.0 specification. This VIP has also been verified for protocol compliance using asureSIGN, T&VS’ in-house Requirements Management and Tracking tool.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by T&VS and successfully deployed by leading SoC companies around the world.
T&VS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
- VIP: AMBA APB Master or Slave
- Compliance: AMBA APB version 4.0 / 3.0
- Language: System Verilog
- Methodology: OVM 2.1.1 / UVM 1.1
- Simulators: Cadence Incisive, Mentor Questa, Aldec Riviera-PRO
APB VIP Deliverables
- APB Master or Slave VIP
- Sample Virtual Sequencer
- Sample Scoreboard
- VIP User Guide
The following features are supported:
- Configurable DataSize
- Configurable PSELx
- Unaligned Address access
- Valid PREADY Detection
- Slave Error Detection
- With No wait Transfer
- With wait Transfer
- User data load via backdoor access
- asureVIP AMBA APB VIP Datasheet
Find out more
For more information or to discuss you requirements, please Contact Us.
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