CSIX VIP

CSIX VIP (Common Switch Interface Verification IP)
The CSIX VIP (Common Switch Interface) is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting UVM, this CSIX VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.

The CSIX VIP can be used for both functional verification and as an emulator and provides the capability to communicate over 32 bit CSIX bus. The VIP comes with a UVM Monitor for checking the conformance of the design with the technical specifications. The monitor performs the protocol checks and reports errors for noncompliance of features with CSIX-L1 bus specification. T&VS CSIX transactor comprises of a synthesizable hardware part written in System Verilog and a software part written in C++ and System Verilog.

Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by T&VS and successfully deployed by leading SoC companies around the world.

T&VS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.

Overview

  • VIP: CSIX
  • Compliance: CSIX-L1 1.0
  • Language: System Verilog
  • Methodology: UVM 1.1
  • Simulators: Cadence Incisive, Mentor Questa, Aldec Riviera-PRO

CSIX VIP Deliverables

  • CSIX VIP
  • Sample Testbench integrated with proven XILINX CSIX core
  • Sample Scoreboard
  • Sample Virtual Sequencer
  • VIP User Guide

Technical Specifications

The CSIX VIP supports:

  • Compatible with Data and Control type CFRAMES
  • Compatible with different Data CFRAME formats IDLE & NORMAL
  • Supports Maximum Configurable Payload Size
  • Supports NORMAL CFRAME Types (Unicast, Multicast, Broadcast)
  • Supports Flow Control CFRAME
  • Supports Link Level Flow Control and Fabric Flow Control
  • Support Pause and Resume Operation for (Link level Flow Control)
  • Generation of Vertical Parity
  • Generation of Horizontal Parity
  • Error Detection for Vertical & Horizontal Parity
  • Synchronous Clock (for interface size 64, 96,128)
  • Supports Error Insertion for Vertical and Horizontal Parity
  • Callback Support to inform Received & Transmitted Packet Information to the User

Datasheet Download

Find out more

For more information or to discuss you requirements, please Contact Us.

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