The SPDIF VIP (Sony/Philips Digital Interface Format) is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting UVM, this Master and Slave SPDIF VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.
The Master VIP has been interoperability tested with a Slave VIP configuration with the slave VIP used in successfully verifying a DUT and later silicon proven. The VIP comes with a Monitor for performing all protocol checks. The monitor also performs key protocol checks and reports errors for non compliance with IEC Specification.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by T&VS and successfully deployed by leading SoC companies around the world.
T&VS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
- VIP: SPDIF Master and Slave
- Compliance: IEC Specification
- Language: System Verilog
- Methodology: UVM 1.1b
- Simulators: Cadence Incisive, Mentor Questa, Aldec Riviera-PRO
SPDIF VIP Deliverables
- SPDIF Master or Slave VIP
- Sample Testbench (Integrated with proven SPDIF Slave VIP)
- Sample Virtual Sequencer
- Sample Scoreboard
- VIP User Guide
The SPDIF VIP supports:
- Supports 2 pin configuration
- Supports Two Modes: System Clock and Internal clock
- Supports both Transmitter and Receiver
- Linear PCM Encoded Audio Bit stream
- Non-Linear PCM Encoded Data burst with AC-3, Enhanced AC-3,DTS-I,DTS-II,DTS-III,DTS-IV
- Channel Coding Technique – BMC
- BMC – Bi-Phase Mark Coding
- asureVIP SPDIF VIP Datasheet
Find out more
For more information or to discuss you requirements, please Contact Us.
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