The SPI VIP (Serial Packet Interface) is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting UVM, this SPI VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.
The SPI VIP provides capability to communicate over SPI bus with the SPI transactor comprising a synthesizable hardware component written in System Verilog and a software part written in C++ and System Verilog. The VIP comes with a UVM Monitor for checking the conformance of the design with the technical specifications, performing the protocol checks and reporting compliance errors.
Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by T&VS and successfully deployed by leading SoC companies around the world.
T&VS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.
- VIP: SPI
- Compliance: OIF-SPI-4-02.1
- Language: System Verilog, C or C++
- Methodology: UVM 1.1
- Simulators: Cadence Incisive, Mentor Questa, Aldec Riviera-PRO
SPI VIP Deliverables
- SPI 4.2 VIP
- Sample Testbench Integrated with proven XILINX SPI CORE
- Sample Scoreboard
- Sample Virtual Sequencer
- VIP User Guide
The SPI VIP supports:
- Point-to-Point Connection (i.e., between single PHY and single Link Layer device)
- Support for 256 ports
- 16 bits wide Transmit / Receive Data Path
- In-band port address
- Start / End-of-packet indication
- Error-control code
- Supports randomization of training sequence
- Supports SOP spacing
- Transmit / Receive FIFO Status Interface
- 2-bit parallel FIFO Status indication
- asureVIP SPI VIP Datasheet
Find out more
For more information or to discuss you requirements, please Contact Us.
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