T&VS is presenting on M-PHY Analog Modelling and Verification at DVCon India

At DVCon India Mallikarjuna Reddy, Venkatramana Rao and Somanatha Shetty from T&VS are presenting on ‘M-PHY Analog blocks Modelling and Verification using SV/UVM-MS'. In this presentation, T&VS explore how application of advanced AMS modelling techniques help in minimizing the run time significantly for mixed signal designs .T&VS also present benefits of developing SV/UVM-MS environment for [...]

2015-09-07T07:22:34+00:007th September, 2015|Active Event, Blog, Events|

When Are You Done With Analog Verification?

In this article Bryan Bailey contrasts the metrics driven verification approach we take in digital with the approach taken in analog verification. However, I personally see some improvements in the way analog verification is performed. TVS recently applied a UVM approach to verification of an analog design UVM-MS. You can read the article here.

2015-03-26T07:03:26+00:0026th March, 2015|Blog, Thought Leadership|