Eliminating manual work during power intent verification of analog IPs reduces susceptibility to risks created by human error. This article from Design Reuse describes how designers can quickly and accurately verify the power models for the analog IP blocks with an automated power model verification process. Read More Learn how T&VS automate power model verification [...]
Most of the bugs in analog circuits can be avoided by defining the optimal design margins, following strict verification procedures, and adhering to guidelines. Finding the right trade-off is a moving target that changes with technology and market priorities. This article from EDN outlines the steps that are followed in the automotive microcontroller division in [...]
The October 2012 DVClub takes place on Monday 8th. The line-up is: Mathieu Behaghel of ST Ericsson speaking on Digital to Mixed-Signal Verification of Power Management SOCs Using Questa-ADMS Jeganath Gandhi Rajamohan of Test and Verification Solutions speaking on Practical Verification of AMS SoCs Abhisek Verma of Synopsis speaking on Extending UVM Methodology for Verifying [...]
DVClub on Monday 6th December 2010 considered AMS verification.