Eliminating manual work during power intent verification of analog IPs reduces susceptibility to risks created by human error. This article from Design Reuse describes how designers can quickly and accurately verify the power models for the analog IP blocks with an automated power model verification process.
Learn how T&VS automate power model verification for analog IPs
Most of the bugs in analog circuits can be avoided by defining the optimal design margins, following strict verification procedures, and adhering to guidelines. Finding the right trade-off is a moving target that changes with technology and market priorities. This article from EDN outlines the steps that are followed in the automotive microcontroller division in order to fully verify analog IPs.
The October 2012 DVClub takes place on Monday 8th. The line-up is:
- Mathieu Behaghel of ST Ericsson speaking on Digital to Mixed-Signal Verification of Power Management SOCs Using Questa-ADMS
- Jeganath Gandhi Rajamohan of Test and Verification Solutions speaking on Practical Verification of AMS SoCs
- Abhisek Verma of Synopsis speaking on Extending UVM Methodology for Verifying Mixed-Signal Components.
Why not register to hear these speakers bring their own unique perspective.
Registration and additional details of the presentations and speakers can be found through the link.
DVClub is organised by TVS who are committed to making DVClub FREE and accessible to everyone and you can join the meeting remotely via the internet or physically in several locations:
- Remote Access
If you attend remotely why not do what many other companies do – book a room and invite your colleagues along so you can discuss and debate the topic.