Tag Archives: ASIC Verification

Understanding ASIC Development

Developing an ASIC or a SoC and going into production require various competences. As a result, it is necessary to ensure that the ASIC design and development process is undertaken in a logical and controlled manner. Each stage of the ASIC design and development process should be carefully monitored, and precautions taken to ensure that the final ASIC design meets the requirement and operates satisfactorily in real world applications.

This article from Any Silicon summarizes the development stages of ASIC design and outlines the several types of ASIC development. Read More


Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.

Improving ASIC Design Verification using FPGAs and Structured ASICs

Prototyping an ASIC or SoC design using FPGAs can relieve the time bottleneck and remove the high calibre compute resources required to verify the functionality of medium-to-large sized designs. This article from Design Reuse describes the benefits of using FPGAs and structured ASICs to improve verification of ASIC or SoC designs in less time, thereby reducing the overall risks of ASIC or SoC development.

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Learn T&VS services that help you know why FPGA technology is making new inroads as demands increase for better integration between hardware and software.

ASIC Verification: Build or Simulate?

Managing verification for ASICs requires a well-defined verification plan. Efficient verification planning starts with functional and design requirements in which requirements are mapped to verification methods, scenarios, and coverage groups. This article from Any Silicon describes the recommended verification approaches in building or simulating the ASIC verification by defining their advantages and issues.

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