High-level Synthesis is an automated design process that lets hardware architects to build and verify hardware efficiently. This article from SemiWiki describes how HLS/HLV methodology works efficiently at a higher level (C/C++/SystemC) and complements the RTL flow for ASIC design productivity.
Learn more about T&VS SystemC model for the Advanced Memory Subsystem
Frank Schirrmeister, Group Director for Product Marketing at Cadence,explores the benefits of using FPGAs for ASIC Prototyping with the help of two abstraction levels (Transaction-level models (TLM) and Register transfer models (RTL)) and the factors that limit the growth of FPGA based prototyping.
This article from Design and Reuse presents an IP core speech detector for real-time systems, focusing on identification of segments of silence or voice, used in pre-processing of input signals to Speaker Recognition and Verification Systems.
The IP-core was designed to be able to be adapted to different environments of use and based on energy of samples to classify them as voice or silence.
Bristol, UK, 24 November, 2014 – TVS, a leader in software test and hardware verification solutions, today announced its business partnership with ELECTRA IC. The Istanbul, Turkish-based design and verification services company has excellent synergy with TVS and the partnership creates opportunities for both companies to leverage their combined expertise to win and operate projects in Turkey.
Operating in the areas of ASIC, FPGA, PCB and IP/VIP, ELECTRA IC has experience in working with global, multinational companies, working on consumer, automotive, mobile connectivity (WiFi, Bluetooth, GPS) and defence projects since 1995. The company is strong in project management, especially working on DO-254* projects that require first class management and tracing skills. ELECTRA IC also has vast remote team working experience working with global giants such as Alcatel, Northern Telecom, ST, ST-Ericsson and Ericsson.
Complementing its new partner, TVS has expertise in HW/SW test and verification and VIP solutions, and its asureSIGNTM products with respect to DO-254 are particularly apt within the partnership and its expected theatre of operation. Continue reading
Bristol, UK, 8 July, 2014 – TVS, a leader in software test and hardware verification solutions, today announced it is continuing its international expansion through a partnership with TopBrain Design Systems. TopBrain is an advanced verification solutions provider for complex electronics design organisations and this partnership announcement formalises TopBrain as the official partner for all of TVS’ products and services in China.