Maximizing hardware emulation’s value for networking designs

There are challenges unique to designing ASICs for networking applications. One is that bandwidth and latency performance tests for these devices require significantly more simulation cycles than required by other types of ICs. This article explains how to maximize hardware emulation’s value for networking designs. Read More Find out how T&VS Verification services help to meet [...]

2018-11-21T09:39:36+00:0021st November, 2018|Blog, Thought Leadership|

Maximizing hardware emulation’s value for networking designs

There are challenges unique to designing ASICs for networking applications. To address these challenges, engineers have adopted the practice of combining simulation with emulation to both improve and accelerate the verification process. This article shows how to increase hardware emulation’s value for networking designs. Read More Find out how T&VS Verification services help to meet the [...]

2018-11-02T06:32:45+00:002nd November, 2018|Blog, Thought Leadership|

Implementing floating-point algorithms in FPGAs or ASICs

Floating-point is the most preferred data type to ensure high-accuracy calculations for algorithm modeling and simulation. This article explores how to implement floating-point algorithms in FPGAs or ASICs. Read More Check out T&VS services that help you know why FPGA technology is making new inroads as demands increase for better integration between hardware and software.

2018-06-29T07:06:33+00:0029th June, 2018|Blog, Thought Leadership|

Leveraging HLS/HLV flow for ASIC Design productivity

High-level Synthesis is an automated design process that lets hardware architects to build and verify hardware efficiently.  This article from SemiWiki describes how HLS/HLV methodology works efficiently at a higher level (C/C++/SystemC) and complements the RTL flow for ASIC design productivity. Read More Learn more about T&VS SystemC model for the Advanced Memory Subsystem

2016-01-21T06:03:38+00:0021st January, 2016|Blog, Thought Leadership|

A Prototyping with FPGA approach

Frank Schirrmeister, Group Director for Product Marketing at Cadence,explores the benefits of using FPGAs for ASIC Prototyping with the help of two abstraction levels (Transaction-level models (TLM) and Register transfer models (RTL)) and the factors that limit the growth of FPGA based prototyping. Read More

2015-08-17T05:34:32+00:0017th August, 2015|Blog, Thought Leadership|

ASIC Implementation of a Speech Detector IP-Core for Real-Time Speaker Verification

This article from Design and Reuse presents an IP core speech detector for real-time systems, focusing on identification of segments of silence or voice, used in pre-processing of input signals to Speaker Recognition and Verification Systems. The IP-core was designed to be able to be adapted to different environments of use and based on energy [...]

2015-04-10T04:58:06+00:0010th April, 2015|Blog, Thought Leadership|

TVS’ partnership with ELECTRA IC strengthens Turkish presence

PRESS RELEASE Bristol, UK, 24 November, 2014 – TVS, a leader in software test and hardware verification solutions, today announced its business partnership with ELECTRA IC. The Istanbul, Turkish-based design and verification services company has excellent synergy with TVS and the partnership creates opportunities for both companies to leverage their combined expertise to win and [...]

2018-02-16T11:33:31+00:0024th November, 2014|Press Releases, Thought Leadership|

TVS extends products and services into China in partnership with TopBrain Design Systems

PRESS RELEASE Bristol, UK, 8 July, 2014 – TVS, a leader in software test and hardware verification solutions, today announced it is continuing its international expansion through a partnership with TopBrain Design Systems. TopBrain is an advanced verification solutions provider for complex electronics design organisations and this partnership announcement formalises TopBrain as the official partner [...]

2016-10-25T05:53:02+00:008th July, 2014|Press Releases, Thought Leadership|