Tag Archives: assureSIGN

DVCon Europe 2015 to focus on functional safety and innovative verification methods

Building on the success of last years’ inaugural event, DVCon Europe 2015 promises to be bigger and better than ever.For this year’s conference, in addition to the more obvious practices and trends in design and verification, there is a clear focus on functional safety and innovative verification methods, addressing verification at both the IP and system levels. The automotive space is a prominent application domain at DVCon Europe, which is well reflected by introducing a separate track on functional safety, the keynote on automotive issues and trends, and, new this year, a plenary panel session on the automotive semiconductor value chain.

Mike Bartley, CEO of TVS, has been on the DVCon Europe Technical Program Committee for both 2014 and 2015. TVS, a leader in functional safety and innovative verification methods, will therefore have a strong presence at DVCon:

  • Tutorial: Verifying Functional, Safety and Security Requirements (for Standards Compliance)
  • Panel: The Functional Verification Roadmap: Where will we be in Five Years?
  • Poster: A SystemC-based UVM Verification Infrastructure
  • Exhibiting: Stand F2 where you can learn how asureSIGN supports your ISO26262 compliance.

For full details visit the TVS website.

DVCon Europe is a fantastic networking event for design and verification professionals, to meet their peers, as well as EDA, IP and training partners, all under one roof. There is also a rich and diverse exhibition with many well-known and new tool and service providers from around our industry.

This is becoming the premier European event to learn about the latest practices, tools and techniques for IC design and verification. Please look further at the site www.dvcon-europe.org and sign up now!

TVS will be Exhibiting at DVCon Europe November 11-12 at Munich

TVS have a strong presence at DVCON Europe this year. TVS will be presenting a tutorial, participating in a panel, chairing the poster session, presenting a poster as well as exhibiting.

Tutorial: Verifying Functional, Safety and Security Requirements

Panel: The Functional Verification Roadmap: Where will we be in Five Years?

Poster: A SystemC-based UVM Verification Infrastructure

If you’re visiting DVCon Europe please check out these two sessions and come along to our stand for the latest solution demos and announcements; including the latest updates to asureSIGN, our leading-edge leading Requirements Driven Verification tool – or simply stop by for a chat, it will be great to meet you.

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Safety, Requirements Engineering and Proof of Implementation

Serrie-justine Chapman, asureSIGN Product Manager and Requirements Engineering Consultant at TVS, recently spoke on “Safety Standards and how they affect the design and verification community” at the DVClub Europe Conference which took place on 20 October 2015.

The Presentation Slides of “Safety, Requirements Engineering and Proof of Implementation” are available now