Tag Archives: asuresign

TVS will be at NATEP to discuss “Avionics Safety guidelines” on 12 November 2015

NATEP is a national programme under which aerospace supply chain companies are developing more than 100 new technologies for the UK and global aerospace industry.

As one of the first recipients of a NATEP grant, TVS will be at the event to talk about its asureSIGN requirements and verification management product and its extension to provide integrated support for the development of hardware, software and systems under avionics safety guidelines DO-254, DO-178B/C and ARP4754. TVS will also have a stand there where attendees can find out more about what TVS and asureSIGN can offer in the aerospace sector.

It promises to a busy and informative new technology event with participating companies, potential customers and other aerospace industry stakeholders all in attendance.

Event summary:

The very first NATEP Showcase event will celebrate the success of a number of the participating companies and provide an opportunity for them to present their new technologies to the wider world. In addition to this, higher-tier and customer aerospace companies that are supporting NATEP projects will explain why companies ranging from Rolls-Royce, Airbus and Agusta Westland to UTC, Meggitt and Cobham are behind NATEP.

New release of asureSIGN to support Requirements Management and Signoff

TVS is pleased to announce that the May release of asureSIGN is now available with 3 major new features: a Doors interface via a ReqIF interface, a history feature (to track changes in requirements, test plans, etc.) and improved multi-user support.

asureSIGN is a flexible tool which can be used for the following:

  • Requirements Management: Top level Requirements are captured, refined into sub features and atomic level features.
  • Verification management: High level Test plans are captured and linked to the atomic level features outlined above. The test plan can be refined to atomic level test plans. Hence, requirements are mapped to test plans and vice-versa. Test results are captured during the project allowing users to track test plan progress and hence requirements sign-off.
  • Standards compliance: Proof of implementation of requirements through test results as required by the standards or guidelines which are mandatory for industries such as automotive, avionics, defence, rail, nuclear, industrial, etc.

Future 2015 releases will include better integration with Simulink and Jira; improved analysis of the impact of proposed changes; as well as Qualification Kit for avionics, automotive, etc.

You can request your evaluation by emailing [email protected]

Read more.

A SystemC-based UVM Verification infrastructure

TVS recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless baseband IP for advanced WiGig applications.

Blu Wireless follows a SystemC-based design flow. Following an initial specification period, it was quickly agreed that the best approach would be to deploy a SystemC test bench that would be UVM-compliant with a TLM-2.0 interface.

This EDN network blog outlines the infrastructure that was developed and the deployment of that infrastructure to enact the constraint-based random verification.

Read more.

TVS announce major release of asureSIGN

TVS is pleased to announce that the March release of asureSIGN (now being used by existing asureSIGN clients) is now available for evaluation by prospective clients. asureSIGN is a flexible tool which can be used for the following:

  • Verification management: High level Test plans, these may then be further refined into atomic level test plans directly relating to either a single or multiple tests.
  • Requirement Management: Top level Requirement features are listed, these are further refined into sub features and atomic level features which can then map to test plans as above.
  • Standards compliance: Proof of implementation of requirements through test results as required by the standards or guidelines which are mandatory for industries such as automotive, avionics, defence, rail, nuclear, industrial, etc.

The March release adds custom attributes (allowing users to define status, priorities and DAL/ASIL levels for requirements, features, verification goals), the ability to merge results from multiple sources (formal verification, simulation, software tests, coverage, etc.), improved program management (asureVIEW which can give a single verification summary across multiple HW/SW projects) and improved facilities to manage Requirements, Features, Goals and Verification Metrics.

Future 2015 releases will include better integration with Doors, Simulink and Jira; storage of the history of changes to Requirements, Features, Goals and Verification Metrics; improved analysis of the impact of proposed changes; as well as Qualification Kit for avionics, automotive, etc.

Read more.

You can request your evaluation by emailing TVS at [email protected] .

TVS’ partnership with ELECTRA IC strengthens Turkish presence

PRESS RELEASE

Bristol, UK, 24 November, 2014 – TVS, a leader in software test and hardware verification solutions, today announced its business partnership with ELECTRA IC. The Istanbul, Turkish-based design and verification services company has excellent synergy with TVS and the partnership creates opportunities for both companies to leverage their combined expertise to win and operate projects in Turkey.

Operating in the areas of ASIC, FPGA, PCB and IP/VIP, ELECTRA IC has experience in working with global, multinational companies, working on consumer, automotive, mobile connectivity (WiFi, Bluetooth, GPS) and defence projects since 1995. The company is strong in project management, especially working on DO-254* projects that require first class management and tracing skills. ELECTRA IC also has vast remote team working experience working with global giants such as Alcatel, Northern Telecom, ST, ST-Ericsson and Ericsson.

Complementing its new partner, TVS has expertise in HW/SW test and verification and VIP solutions, and its asureSIGNTM products with respect to DO-254 are particularly apt within the partnership and its expected theatre of operation. Continue reading

T&VS to champion Requirements Driven Verification and Test at DVCon Europe

dvcon1

PRESS RELEASE

Bristol, UK, 29 September 2014 – T&VS, a leader in software test and hardware verification solutions, today announced that is presenting and exhibiting at the inaugural Design & Verification Conference and Exhibition Europe (DVCon Europe) to be held in Munich on 14-15 October 2014 at the Hilton City hotel. The company will be showcasing its driven verification and analogue mixed-signal (AMS) capabilities, together with other product developments.

DVCon Europe is a new conference for the application of software languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. DVCon has run successfully for over twenty years in Silicon Valley, so event organisers are expecting a great deal of interest in the first DVCon Europe.

At DVCon Europe, T&VS will be presenting two papers and one tutorial:

  • T&VS’s tutorial: ‘Requirements Driven Verification and Test (RDVT)’ will be on Tuesday October 14th at 11.30-13.00 and will outline what the development standards mandate and how they can be delivered through requirements-driven verification methodology.
  • T&VS’s first paper: ‘Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVM Verification’ will take place on Wednesday 15 October at 11.30-12 to be presented by T&VS’s Suresh Babu in partnership with Roman Wang of AMD.
  • T&VS’ second paper: ‘Requirements-Driven Verification Methodology (for Standards Compliance)’ will be held later the same day at 16.00-17.00 to be presented by T&VS’s Mike Bartley and Serrie Chapman.

On its DVCon Europe booth, Stand 1, T&VS will be showcasing its latest capabilities and product developments:

  • asureSIGN is a tool for managers, developers and integrators that ensures that product requirements have been successfully tested and implemented.
  • asureCOMPLY makes compliance easier with effective verification in the of safety standards compliance.
  • AMS VIP (Analogue Mixed-Signal Verification IP), offered as part of T&VS’
    asureVIP portfolio, is a suite of tools to provide an efficient, re-usable, development strategy that delivers verification, architecture IP, coverage collection and signoff of AMS designs.

Mike Bartley, CEO of T&VS and DVCon Chair, stated, “Visitors are invited to check out our tutorial and technical talks or come along to our stand for the latest solution demos and announcements; including asureSIGN, our leading-edge leading Requirements Driven Verification tool and our analogue mixed-signal capabilities – or simply stop by for a chat.”

If you’d like to prearrange a meeting at the event please email Mike Bartley of T&VS at: [email protected]

About T&VS
T&VS (Test and Verification Solutions Ltd) provides services and products to organisations developing complex products in the microelectronics and embedded systems industries. Such organisations use T&VS to verify their hardware and software products, employ industry best practice and manage peaks in development and testing programmes. T&VS’ embedded software testing services includes onsite/offshore testing support including assistance with safety certification and security testing. T&VS hardware verification services include onsite/offshore verification support and training in advanced verification methodologies. T&VS also offers Verification IPs and its own Verification (EDA) signoff tool.

T&VS Company Contact
Dr. Mike Bartley – T&VS
+44 7796 307958
[email protected]

Media Contact
Oliver Davies – Publitek Technology PR
+44 1225 470000
[email protected]