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RTL CDC Is No Longer Enough — How Gate-Level CDC Is Now Essential to First Pass Success

Clock-domain crossing (CDC) verification is a critical step in the design verification cycle. However, CDC verification is not only necessary on RTL; at 28nm nodes and below it is also essential on gate-level designs due to the possibility of the introduction of CDC errors during the synthesis phase that can lead to silicon failure. This [...]

2017-08-02T03:55:34+00:002nd August, 2017|Blog, Thought Leadership|

CDC Verification for FPGA – Beyond the Basis

Due to the growth in complexity of FPGAs and integration of complex IP, the number of asynchronous clocks within FPGA designs has dramatically increased. It has become increasingly difficult to verify these designs for metastability issues due to asynchronous clock domain crossings (CDC). Clock domain crossings are a key cause of non-deterministic & random field [...]

2017-05-31T07:32:40+00:0031st May, 2017|Blog, Thought Leadership|

Domain Crossing Verification Needs Continue to Grow

This article from SemiWiki describes how Clock Domain Crossing (CDC) solution enables comprehensive clock and reset domain crossing (CDC/RDC) verification for more than a billion gates, helping designers to avoid costly chip killer bugs, re-spins and achieve signoff quality verification. Read More Learn more about how T&VS helps engineers to set up the correct methodology [...]

2016-07-04T05:54:30+00:004th July, 2016|Blog, Thought Leadership|