Tag Archives: CDC verification

RTL CDC Is No Longer Enough — How Gate-Level CDC Is Now Essential to First Pass Success

Clock-domain crossing (CDC) verification is a critical step in the design verification cycle. However, CDC verification is not only necessary on RTL; at 28nm nodes and below it is also essential on gate-level designs due to the possibility of the introduction of CDC errors during the synthesis phase that can lead to silicon failure.

This article from Mentor Graphics review the root cause of these challenges and introduce an automated approach to overcome these difficulties.

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CDC Verification for FPGA – Beyond the Basis

Due to the growth in complexity of FPGAs and integration of complex IP, the number of asynchronous clocks within FPGA designs has dramatically increased. It has become increasingly difficult to verify these designs for metastability issues due to asynchronous clock domain crossings (CDC).

Clock domain crossings are a key cause of non-deterministic & random field failures in FPGA based systems, leading to unnecessary cycles of design and debug costing designers both valuable time and resources. This article from Semiwiki describes how to address CDC issues early at RTL for FPGA designs, saving valuable time and costly design re-spins.

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Domain Crossing Verification Needs Continue to Grow

This article from SemiWiki describes how Clock Domain Crossing (CDC) solution enables comprehensive clock and reset domain crossing (CDC/RDC) verification for more than a billion gates, helping designers to avoid costly chip killer bugs, re-spins and achieve signoff quality verification.

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Learn more about how T&VS helps engineers to set up the correct methodology in order to achieve the zero errors while running CDC verification.

CDC Verification of Fast-to-Slow Clocks –Structural Checks

CDC checking of any asynchronous clock domain crossing requires that the data path and the control path be identified and that the receive clock domain data flow is controlled by a multiplexer with a select line that is fed by a correctly synchronized control line.

The structural checking approach does not care if the asynchronous transitions are slow to fast clocks or fast-to-slow clocks.  It will ensure that all the transitions are correctly synchronized in terms of having the appropriate synchronizer flops.

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