Tag Archives: debug and trace

DAC2014 : A Perspective on Verification (blog for EDN)

edn-network-logoIn a recent blog for EDN, Karthik Nagappan (general manager of T&VS India) shared his perspective on DAC2014 and the latest developments in Verification. A short abstract of the article is enclosed below. To read the full article visit EDN Network.

karthik-nagappan-webOne of the many sessions at DAC this year was looking beyond functional verification to the challenges in non-mainline verification. This can take up to 30% of the total verification effort, so as the verification challenge grows, so do the non-mainstream elements, such as initialization and reset sequences, reliability, power management, built in self test (BIST) mechanisms, and debug and trace logic. Despite advances in automating formal functional verification using “apps” built into most formal verification tools, non-mainline verification is characterized by ad-hoc and manual methods, and the absence of methodologies, technologies, and tools.

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