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Debugging Debug

Debug is more than just ensuring that functionality is correct. It includes every aspect of design that involves writing a description, making a decision, or guiding a tool potentially introduces errors. This article from Semiengineering explores whether the time spent on debug can reduce or not. Read More Find out how T&VS have developed a [...]

2018-02-28T06:05:08+00:0028th February, 2018|Blog, Thought Leadership|

Debug: Last Bastion Of Automation

Debug is a challenge for the semiconductor industry. Due to increased design complexity, it consumes a higher percentage of development time. Moreover, it is not just limited to verification. This article from Semi Engineering describes why debug consumes 50% of development time and resources. Read More Learn more about T&VS Hardware Verification

2016-02-09T06:03:51+00:009th February, 2016|Blog, Thought Leadership|

Solutions to Resolve Traditional PHY Verification Challenges

PHYs are present in multiple domains – be it memory (DDR2/DDR3/DDR4/LPDDR3), Ethernet, SATA, USB or PCIe. This article from Mentor Graphics describes various techniques and solutions to resolve PHY verification challenges. The solution incorporates a host of benefits, including faster, more flexible verification and easier debugging. Read More Learn more about T&VS MIPI D-PHY VIP

2016-01-14T06:21:37+00:0014th January, 2016|Blog, Thought Leadership|

Minimizing Constraints to Debug Vacuous Proofs

Most of the design bugs missed during the practice of model checking on industrial designs can be reduced to the problem of a failing cover. When the formal testbench has many constraints, debugging the root cause of such a failing cover can be a laborious process. This article from Mentor Graphics describes a method to [...]

2015-12-10T05:22:08+00:0010th December, 2015|Blog, Thought Leadership|

Cadence Introduces Indago Debug Platform

The Cadence Indago Debug Platform is a new debugging solution which reduces the time to identify bugs in a design by up to 50 percent compared to traditional signal- or transaction-level debug methods. The Indago platform and associated debugging apps are currently available for early adopters. Read more.

2015-05-22T05:25:10+00:0022nd May, 2015|Blog, Thought Leadership|

Why Gate-Level Simulation is increasing

This article from Cadence explains the results of a survey involving verification engineers from 7 major Cadence customers located in North America, Japan, India and Europe.  The survey highlighted that process nodes mostly ranged from 28nm to 45nm and cited the top reasons for running gate-level simulation. A separate question about DFT simulation revealed that [...]

2015-09-21T13:00:47+00:0024th March, 2015|Blog, Thought Leadership|

We need to solve the debug challenge

I have mentioned in numerous articles and blogs that I think debug is currently our biggest challenge but the one that sees the least innovation in tooling. Assertion-based verification has been the biggest advance in debugging but we can hardly claim it was an innovation in tolling – more a side product of a really [...]

2015-03-23T05:56:59+00:0023rd March, 2015|Blog, Thought Leadership|