This article from Semiengineering brief about a conversation between low power debug experts to complete the typical debugging scenarios by static checking, dynamic checks, and dynamic sequencing.
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Debug is a challenge for the semiconductor industry. Due to increased design complexity, it consumes a higher percentage of development time. Moreover, it is not just limited to verification. This article from Semi Engineering describes why debug consumes 50% of development time and resources.
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Finite state machines (FSMs) are a familiar and frequently used technique in electronic systems design, but are error prone as well. This article from Tech Design Forum outlines how to debug and verify FSMs early in the design flow.
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PHYs are present in multiple domains – be it memory (DDR2/DDR3/DDR4/LPDDR3), Ethernet, SATA, USB or PCIe. This article from Mentor Graphics describes various techniques and solutions to resolve PHY verification challenges. The solution incorporates a host of benefits, including faster, more flexible verification and easier debugging.
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Most of the design bugs missed during the practice of model checking on industrial designs can be reduced to the problem of a failing cover. When the formal testbench has many constraints, debugging the root cause of such a failing cover can be a laborious process. This article from Mentor Graphics describes a method to minimize the number of model checking runs to identify a minimal failing subset (MFS) of constraints. This solution has increased the productivity by reducing the iterations required to debug vacuous proofs.
The Cadence Indago Debug Platform is a new debugging solution which reduces the time to identify bugs in a design by up to 50 percent compared to traditional signal- or transaction-level debug methods.
The Indago platform and associated debugging apps are currently available for early adopters.
Synopsys founder says TVS has been arguing shift-left for many years. It is already popular in software and can be summarized as “moving the testing effort as early in the development process as possible”.
TVS also argues for such an approach in hardware development too and believes this can be achieved by the “Requirements Driven Test and Verification” approach promoted by TVS.
This article from Cadence explains the results of a survey involving verification engineers from 7 major Cadence customers located in North America, Japan, India and Europe. The survey highlighted that process nodes mostly ranged from 28nm to 45nm and cited the top reasons for running gate-level simulation. A separate question about DFT simulation revealed that about half of respondents use this technique to verify scan chains.
I have mentioned in numerous articles and blogs that I think debug is currently our biggest challenge but the one that sees the least innovation in tooling. Assertion-based verification has been the biggest advance in debugging but we can hardly claim it was an innovation in tolling – more a side product of a really useful verification technique.
So I was heartened to see a panel on “Discuss Verification Debug Challenges and Strategies” at DVCon chaired by Brian Bailey.
John Goodenough, VP of Engineering Systems at ARM, summarized well the 2 major issues: first, we need to reduce the latency of the time-to-triage and root-cause analysis and subsequent fixing; secondly we don’t want to make the same mistake again.
Read the whole article here.