Tag Archives: Design and verification

MIPI UniPro Stack based Design and Verification

Mobile phone market is very competitive and time to market is very critical for mobile system designs. It becomes important that the IP design and verification cycle is continuously optimized. MIPI UniPro is a layered protocol for interconnecting devices within a mobile system and allowing them to exchange information at high-data rates. This article describes the various verification topologies possible in a UniPro design and stack based architecture of Synopsys UniPro VIP.

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Find out how T&VS MIPI UniPro Verification IP de-risks your MIPI UniPro development effort by providing a high degree of confidence over all the design features.

Reaching Coverage Should be Science Not Art

“Coverage Closure” is the process used to reach 100% of your coverage goals. In a directed test methodology, it is simply the process of writing all of the test cases outlined in the verification plan.

Adiel Khan, Senior Staff Engineer at Synopsys, will discuss “why Reaching Coverage should be Science not Art” at DVClub Europe Conference on 1 December 2015.

Attending the DVClub conference on December1st is free but places are limited so we recommend early registration.

You can register here

Reaching Coverage Should be Science Not Art

In his forthcoming talk at DVClub Europe on Tuesday 1st December, Adiel Khan (Senior Staff Engineer, Verification Group Business Unit) at Synopsys will discuss using graph based portable stimulus in system level coverage closure.

“Coverage Closure” is the process used to reach 100% of your coverage goals. In a directed test methodology, it is simply the process of writing all of the test cases outlined in the verification plan.

For RTL-Code coverage this is ensuring all lines and conditions of code have been executed. In a constrained-random methodology, it is the process of adding constraints, defining scenarios or writing directed tests to hit the uncovered areas in your functional and structural coverage model. In the latter case, it is a process that is time-consuming and challenging: you must reverse-engineer the design and verification environment to determine why specific stimulus must be generated to hit those uncovered areas.

Something that is challenging and time-consuming is an ideal candidate for automation. In this case, the Holy Grail is the automation of the feedback loop between the coverage metrics and the required stimulus. The challenge in automating that loop is correlating those metrics with the input constraints, rather than leaving the engineer to draw out and hypothesize on possible ways to reach that coverage metric.

See the full agenda and registration details here

About DVClub

The principal goal of DVClub Europe is to have fun while helping build the verification community through regular educational and networking events.  Attendance is free and can be in-person by attending one of three European venues or via remote access.  Attendance is open to all non-service provider semiconductor professionals but registration is essential as these sessions are often over-subscribed.  DVClub Europe is coordinated by TVS with the support from a number of sponsors.

Discuss the latest in verification with T&VS at DVCon India 2015!

T&VS have a strong presence at DVCon India this year. Dr. Mike Bartley, founder and CEO, is serving on the panel for the session ‘Supporting the Evolving Verification flow’ at DVCon India 2015’ with LauroRizzatti and Sanjay Gupta of Mentor Graphics on 10th September. He is also chairing session D1A1.1-DV of the DV track between 13.30 – 15.00 the same day.

On the 11th, Mallikarjuna, Venkat and Somanatha from T&VS are presenting a paper on AMS Verification titled ‘MIPI M-PHY Analog Modelling with Verilog-AMS (Wreal) and Verification using SV/UVM-MS Methodology’.

Do say hi to Mike, Mallikarjuna, Venkat and Somanatha if you spot them. They will be more than happy to discuss verification with you!

Achieving Compliance with Aviation’s D0-254 without Tears

Dr.Pranav Ashar, CTO of Real Intent, says Compliance with aviation’s hardware design standard is seen as a ‘tough task’, but EDA’s own evolution has made that process easier than you may think. At first glance the DO-254 aviation standard, ‘Design Assurance Guideline for Airborne Electronic Hardware’, seems daunting. It defines design and verification flows tightly with regard to both implementation and traceability.

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