Reflection On 2017: Design And EDA

This article from Semiengineering describes the progress of design and EDA industry for the year 2017 and outlines the predictions for the next year which make us continue to see a focus on software that enables a clear visualization of design workflows, and tools that make it easier for engineers to make component selection and [...]

2018-01-12T05:39:56+00:0012th January, 2018|Blog, Thought Leadership|

Mixing Interface Protocols

Continuous and pervasive connectivity requires devices to support multiple interface protocols, but that is creating problems at multiple levels because each protocol is based on a different set of assumptions. This article from Semiengineering highlights how to ensure that a device can interface with a variety of protocols Read More Find out how T&VS have [...]

2018-01-04T06:42:13+00:004th January, 2018|Blog, Thought Leadership|

PA GLS: The Power Aware Gate-level Simulation

In post-synthesis, gate-level netlist (GL-netlist), power aware (PA) simulation, the fundamental focus is to identify PA specific cells already present in the netlist. The associated UPF with the netlist design, determines the supply network and power connectivity to these special PA cells, and aid to keep their outputs from being corrupted. Hence, the GL-netlist-based power [...]

2018-01-03T07:06:11+00:003rd January, 2018|Blog, Thought Leadership|

How to apply Continuous Integration to Hardware Design and Verification

With agile approaches being applied with success to hardware design and verification development processes, the uncertainty to apply a continuous integration flow in a hardware development process is raised. This article presents the main differences between software development and hardware verification in terms of integration process, and outlines how continuous integration practices can increase the [...]

2017-08-22T12:40:39+00:0024th August, 2017|Blog, Thought Leadership|

Design & Verify Virtual Platform with reusable TLM 2.0

As the system, software & IP complexity is increasing so is the demand of SystemC models & Virtual Platform for verification. To achieve it, the key requirements are that the models/platform should be developed fast, reusable & highly accurate. This article from Design reuse outlines the benefits of generic models and automation techniques which eases [...]

2017-07-26T09:44:33+00:0028th July, 2017|Blog, Thought Leadership|

It’s Time for an Embedded Systems Design Verification Revolution

This article describes why today, the revolution is building in the verification space and outlines how the verification methodologies will roll out over the next two decades, and make the process of silicon realization more efficient and effective. Read More Find out how T&VS Verification services help to meet the challenging requirements with respect to [...]

2017-05-19T06:14:16+00:0019th May, 2017|Blog, Thought Leadership|

Applying Continuous Integration to Hardware Design and Verification

With agile approaches being applied with success to hardware design and verification development processes, the uncertainty to apply a continuous integration flow in a hardware development process is raised. This article presents the main differences between software development and hardware verification in terms of integration process, and outlines how continuous integration practices can increase the [...]

2017-02-08T06:25:50+00:008th February, 2017|Blog, Thought Leadership|

Massively parallel frameworks for in-design verification

In-design verification is needed to shorten design cycles and maximize circuit performance, ensuring physical designs are correct by construction. Physical verification often forces a decision between accuracy and performance for larger designs. Cloud infrastructure needs are pushing the industry toward larger multi-core server architectures and massively parallel computing frameworks. This article explores how these massively [...]

2017-01-31T05:38:26+00:0031st January, 2017|Blog, Thought Leadership|