Tag Archives: Design Verification

Reflection On 2017: Design And EDA

This article from Semiengineering describes the progress of design and EDA industry for the year 2017 and outlines the predictions for the next year which make us continue to see a focus on software that enables a clear visualization of design workflows, and tools that make it easier for engineers to make component selection and placement decisions as form-factors become smaller.

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Find out how T&VS have developed a unique process that enables companies to make continuous improvements to their design and verification environments.

Mixing Interface Protocols

Continuous and pervasive connectivity requires devices to support multiple interface protocols, but that is creating problems at multiple levels because each protocol is based on a different set of assumptions. This article from Semiengineering highlights how to ensure that a device can interface with a variety of protocols

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Find out how T&VS have developed a unique process that enables companies to make continuous improvements to their design and verification environments.

PA GLS: The Power Aware Gate-level Simulation

In post-synthesis, gate-level netlist (GL-netlist), power aware (PA) simulation, the fundamental focus is to identify PA specific cells already present in the netlist. The associated UPF with the netlist design, determines the supply network and power connectivity to these special PA cells, and aid to keep their outputs from being corrupted.

Hence, the GL-netlist-based power aware simulation input requirements are mostly the same as for RTL simulation. This article summarizes how the Questa® power aware simulation tool conducts power aware simulation on the GL-netlist similar to the RTL design.

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Find out how T&VS have developed a unique process that enables companies to make continuous improvements to their design and verification environments.

How to apply Continuous Integration to Hardware Design and Verification

With agile approaches being applied with success to hardware design and verification development processes, the uncertainty to apply a continuous integration flow in a hardware development process is raised.

This article presents the main differences between software development and hardware verification in terms of integration process, and outlines how continuous integration practices can increase the interaction between the verification team and the design team.

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Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.

Design & Verify Virtual Platform with reusable TLM 2.0

As the system, software & IP complexity is increasing so is the demand of SystemC models & Virtual Platform for verification. To achieve it, the key requirements are that the models/platform should be developed fast, reusable & highly accurate.

This article from Design reuse outlines the benefits of generic models and automation techniques which eases and reduces the model verification time without prior requirement of any tools.

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Find out how T&VS have developed a unique process that enables companies to make continuous improvements to their design and verification environments.

It’s Time for an Embedded Systems Design Verification Revolution

This article describes why today, the revolution is building in the verification space and outlines how the verification methodologies will roll out over the next two decades, and make the process of silicon realization more efficient and effective.

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Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.

Applying Continuous Integration to Hardware Design and Verification

With agile approaches being applied with success to hardware design and verification development processes, the uncertainty to apply a continuous integration flow in a hardware development process is raised.

This article presents the main differences between software development and hardware verification in terms of integration process, and outlines how continuous integration practices can increase the interaction between the verification team and the design team.

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Find out how T&VS enables companies to make continuous improvements to their design and verification environments.

Massively parallel frameworks for in-design verification

In-design verification is needed to shorten design cycles and maximize circuit performance, ensuring physical designs are correct by construction. Physical verification often forces a decision between accuracy and performance for larger designs. Cloud infrastructure needs are pushing the industry toward larger multi-core server architectures and massively parallel computing frameworks.

This article explores how these massively parallel frameworks can be combined with in-design verification methodologies to allow field solvers to provide golden levels of extraction and simulation accuracy at acceptable levels of performance for larger designs.

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Find out how T&VS enables companies to make continuous improvements to their design and verification environments.