Markets such as automotive, avionics, nuclear, medical, rail, industrial, etc. require compliance to stringent development standards to ensure the devices are safe. As more devices become connected then security also becomes increasingly important.
Mike Bartley of TVS, David Kelf from OneSpin Solutions and Dr. Ryan Kastner, co-founder of Tortuga Logic will cover the following topics in detail at DVCon Europe:
- Defining safety requirements related to ECC (Error Code Correction) mechanisms
- Identifying security requirements such as privileged accesses to memory.
- Demonstrating how all requirements can be traced through feature analysis to a verification plan and how that can be traced through to verification execution thus resulting in a proof of implementation for conformance to development standards.
Do say hi to Mike if you spot him. He will be more than happy to discuss DO254 & DO178C compliance with you!
Find out More
Hardware verification has made many advances in recent years: constrained random testing, functional and code coverage, assertion-based verification, metrics-driven verification, formal verification, requirements-based verification, and many more.
As the complexity of FPGA designs used in avionics increases then the need to move away from directed testing to these more advanced techniques becomes more important. However, how do we move to such techniques and still demonstrate compliance to avionics development standards (such as DO254)?
In this workshop which is going to be held on 17 June at Bangalore, T&VS provides an overview of the advanced verification techniques which T&VS have used extensively for a number of years both in ASIC and FPGA development. More importantly, T&VS will show how these techniques can be used in a DO254 compliance flow.
DVCon has been running in Silicon Valley since 1988 but is now going on the road, arriving in Munich, Germany on October 14th and 15th 2014, where it will receive a European makeover. In anticipation, I’ve talked to a number of key people involved to find out what the European slant on DVCon will be.
Accellera Systems Initiative is a sponsor of DVCon who provide design and verification standards including IP-XACT, SystemC, SystemVerilog, UPF, UCIS and UVM. This gives DVCon Europe a strong technical theme and thus a great place for engineers to network.
T&VS will be presenting a tutorial and exhibiting at this year’s DVCon in Europe, so if you’re visiting please check out our tutorial and technical talks or come along to our stand for the latest solution demos and announcements; including asureSIGN, our leading-edge leading Requirements Driven Verification tool – or simply stop by for a chat.
The Design and Verification Conference & Exhibition Europe is a new conference for the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits, more details below.
Read the blog article: “A European Twist to DVCon.”
||DVCon Europe 2014
|T&VS Stand Location:
||Stand #1, Strauss Foyer
||Requirements-driven Verification Methodology for Standards Compliance
Requirements-driven verification is based on ensuring that feature-level requirements are adequately verified by tracing such requirements through to verification tasks. It is similar to Coverage-driven Verification from the sense that it is metric-driven but differs significantly because the metrics derive from requirements rather than verification goals
Requirements-driven verification is also required for compliance with the increasing number of standards that control development of hardware for domains such as automotive (ISO26262) and avionics (DO254). The tutorial will cover what the development standards mandate and how it can be delivered through requirements-driven verification methodology and will use an automotive example (lane crossing) to cover the three main issues regarding standards compliance and how they are covered through a requirements-driven verification methodology.
Read the Full Tutorial Details on the DVCon Europe website.
|T&VS Talk #1:
||Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVM Verification
- Wednesday, Oct 15, 11:30-12:30 [Session T2.4: Advanced Verification]
- Presented by: Suresh Babu (Test and Verification Solutions) and Roman Wang (AMD)
|T&VS Talk #2:
||Requirements-Driven Verification Methodology (for Standards Compliance)
- Wednesday, Oct 15, 16:00-17:00 [Session T7.2: Verification Management]
- Presented by: Serrie Chapman and Mike Bartley – Test and Verification Solutions
|T&VS Talk #3:
||A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog AMS
- Wednesday, Oct 15, 10:00-11:00 [Session T1.2: Analog / Mixed-Signal Design and Verification]
- Presented by: Jeganath Gandhi Rajamohan, Mike Bartley – Test and Verification Solutions
About DVCon Europe
The Design and Verification Conference & Exhibition Europe is a new conference for the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, systems designers, software developers and IP integrators the latest methodologies, techniques, applications and demonstrations on the practical use of EDA and IP languages and standards used in electronic design.
For more information visit: http://dvcon-europe.org/conference/dvcon-europe-2014/