The ISO 26262 standard defines straightforward metrics for evaluating the “safeness” of a design by defining safety goals, safety mechanisms, and fault metrics. However, determining those metrics is difficult because evaluating every possible fault is impractical on the size of today’s designs. Formal verification tools have an advantage over other approaches because formal tools have the unique ability to trace cones of influence and eliminate large numbers of irrelevant faults in a process known as fault pruning. Formal tools provide unique capabilities that are essential for any automotive functional safety flow.
Abdel Ayari, Digital Design & Verification Solutions Applications Engineer at Mentor Graphics discussed onhow formal reduces fault analysis for ISO26262 safety verificationat the DVClub Europe Conference- “Methodologies for Rigorous Safety Verification”, which took place on 28th November 2017.
The Presentation Slides and Recordings are now available!
Complex designs achieve ISO26262 via the introduction of Safety Mechanisms to protect against random hardware faults that can cause a violation of a Safety Goal. The challenge is in performing a comprehensive safety analysis of the design, and proving the completeness of the analysis in an efficient manner.
Krishna Priya Chakiat Ramamoorthy from Infineon Technologies was at DVClub Europe Conference on 28th November 2017 and explained how APIS IQ features are innovatively used to identify the potential random hardware faults which can disrupt the function of a design, leading to a failure to meet a safety goal and provided a suggestion on how to link this conceptual analysis to design and verification plans, thus closing the gap between architecture and verification.
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Safety critical development processes, governed by standards such as ISO26262, include the use of fault correction components that protect the device against Random faults that occur naturally during operation. A methodology has evolved that makes use of fault simulation and formal techniques to establish the diagnostic coverage of safe faults, and detect dangerous faults. A significant remaining challenge is the debug of these dangerous faults. While fault simulation can establish fault propagation, Formal can produce a clear detection of dangerous faults, enable their debug, and indicate how a design may be protected against their occurrence.
Jörg Große, Product Manager Safety Critical Solution at OneSpin Solutions, discussed these dangerous fault debug techniques using state-of-the-art formal verification appsat the DVClub Europe Conference- “Methodologies for Rigorous Safety Verification” on 28th November 2017.
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Autonomous driving is becoming real. Coming out of the realm of research, autonomous vehicles are now on roads around you. Safety of these vehicles is an important consideration in their design. How do you make sure that the vehicle is safe enough for you to put your loved ones in it?
Ann Keffer, Product Management Director at Cadence Design Systems, illustrated some challenges that make autonomous vehicles safer and discussed the solutions on how we can overcome these challengesat the DVClub Europe Conference which took place on 28th November 2017.
The Presentation Slides and Videos are available now!
T&VS organized a European DVClub on 28th November 2017 with a focus on “Methodologies for Rigorous Safety Verification”. Speakers were from Mentor Graphics, Cadence, Infineon, and One Spin Solutions and the presentations are now available on the T&VS website.
- Ann Keffer, Product Management Director, Cadence Design Systems
Methodologies for Rigorous Safety Verification
- Jörg Große, Product Manager Safety Critical Solution, OneSpin Solutions
Formal fault analysis for ISO 26262 fault metrics on real world designs
- Krishna Priya Chakiat Ramamoorthy, Lead Concept Engineer, Infineon Technologies UK Ltd
Customizing APIS IQ software for ISO26262 safety analysis – closing the gap from concept to verification
- Abdel Ayari, Digital Design & Verification Solutions Applications Engineer, Mentor, A Siemens Business
How Formal Reduces Fault Analysis for ISO 26262 Safety Verification
The Presentation Slides and Recordings are available here
Due to increasing unpredictability and complexity of systems, circuit SPICE and Fast SPICE simulation cannot deliver verification closure on time. With the demand to have more functionality in today’s designs, the high performance SoC’s should further accommodate Analog and Mixed Signal (AMS) designs. This leads to growing necessity of methodology for accurate and fast verification of AMS designs.
Mallikarjuna Reddy from Test and Verification Solutions and Venkatramana rao from Mindlance Technologies, presented on how to improve the verification performance using real value modelling at the DVClub Europe Conference-“Verifying Analog and Physical Designs”, on 12 September 2017.
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Vireen Vodapalli from ARM Embedded Systems Pvt. Ltd, presented on “Co-Simulation for Functional Equivalence Checking” at the DVClub Europe Conference which took place on 12 September 2017.
The Presentation Sides and Recordings of “Co-Simulation for Functional Equivalence Checking” are now available here
Adam Sherer, Product Management Group Director at Cadence Design Systems, recently spoke on “IoT is IoMSLPT for Verification Engineers” at the DVClub Europe Conference “Verifying Analog and Physical Designs”, on 12 September 2017.
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T&VS organized a European DVClub on 12 September 2017 with a focus on “Verifying Analog and Physical Designs”. Speakers were from Cadence, ARM, and T&VS and the presentations are now available on the T&VS website
Find out Slides and Recordings here
Formal Fault Injection is a verification technique used in safety critical automotive devices as well as other high reliability applications. Safety mechanisms are one of the most critical areas of ISO-26262 compliant automotive designs and their architecture and quality is a key differentiator for various IC providers.
Mark Handover of Mentor Graphics, discussed on the impact of a fault injection safety mechanism for ISO 26262 at the DVClub Europe Conference, “Impact of Safety on Verification”, on 29th November 2016.
The Presentation Slides and Recordings of Formal Fault Injection are available now