Functional safety features are an essential part of automotive system-on-chip development. ISO26262 standard dictates ASIC development process in safety applications like airbag control, electronic stability control. Deva Phanindra Kumar from Analog Devices, has recently spoke on how verification flows should be setup to meet stringent requirements of ISO26262 and covered the verification challenges in verifying [...]
For any chipmaker, one of the biggest bottlenecks in getting their chips to market faster is IP Verification. Companies may choose to use pre-verified hard or soft IP developed by the IP providers which are readily available. Or they may choose to develop their own IP verification infrastructure using advanced verification methodologies such as UVM. [...]
IP/SoC checks are very important in any verification activity. But class-based system verilog used in UVM does not allow concurrent assertions. Thus, in order to implement concurrent assertions, we require non-class based objects like interfaces. But this creates problems of encapsulation and isolation. Surinder Sood of SanDisk presented some pragmatic approaches for encapsulation and operation [...]
IP verification is a very challenging process and it involves expending a great deal of effort in technical understanding, planning, and execution. As designs become larger and more complex, the challenge of verification has become even more difficult. Dinesh Kumar Malviya from Rambus Inc discussed the challenges in IP Verification at the DVClub Bangalore Conference- [...]
Presentation Slides & Recordings of DVClub Bangalore -“IP Verification Challenges”, 11 May 2016 are now available!
T&VS organized a DVClub Bangalore on 11 May 2016 with a focus on “IP Verification Challenges”. Speakers were from Rambus Inc, San Disk, and Broadcom and the presentations are now available on the T&VS website IP Challenges Verification-Dinesh Kumar Malviya, Rambus Chip Technologies Encapsulating Concurrent Assertions in UVM – Surinder Sood, SanDisk Reuse - Key [...]