Challenges with Power Aware Simulation and Verification Methodologies

Divyeshkumar Dhanjibhai Vora of ARM will discuss “Challenges with Power Aware Simulation and Verification Methodologies” at DVClub Europe Conference on 22 September 2015. He discusses about proposed enhancements like integrated PA models, liberty based assertions and UPF macro support using successive refinement, to fill the quality holes in the PA simulation flow. As the modelling [...]

2015-09-21T06:33:49+00:0021st September, 2015|Active Event, Blog, Events|

Low Power Verification with Graph-Based Portable Stimulus

Adnan Hamid, Co-Founder and CTO at Breker Verification Inc., will be at DVClub Europe to discuss “Low Power Verification with Graph-Based Portable Stimulus”. If you are working on “Low Power Verification“ or wish to get yourself acquainted with the latest in Graph-Based Portable Stimulus, this session is a must attend. You can attend physically at [...]

2015-09-21T04:37:55+00:0021st September, 2015|Active Event, Blog, Events|

Successive Refinement: A Methodology for Incremental Specification of Power Intent using UPF

Gabriel Chidolue, Verification Technologist at Mentor Graphics, discusses “A Methodology for Incremental Specification of Power Intent using UPF” at DVClub Europe on 22 September 2015. Gabriel presentation will cover how to use the UPF Successive Refinement methodology in detail, how it can accelerate design and verification with a re-usable IP to System flow, and simplify [...]

2015-09-21T04:48:12+00:0018th September, 2015|Active Event, Blog, Events|

DVClub Europe Conference “Power Aware Verification”, 22 September 2015

TVS is proud to work with Mentor Graphics, ARM, Cadence, Synopsys and Breker to bring the DVClub on Tuesday 22 September.The event will focus on “Power Aware Verification “. You can attend physically (at UWE in Bristol, Cambridge, Grenoble and Sophia) or remotely for free – see here for details and registration. The agenda for [...]

2015-09-18T01:54:59+00:0017th September, 2015|Active Event, Blog, Events|

SoC Design Verification using 3rd party IPs – Challenges & Guidelines

At DVClub Bangalore on 18 June 2015, Vedantham and Prem C K, Members of Technical Staff, AMD are presenting their experiences in using 3rd party IPs for SoC Design Verification. This presentation will cover important considerations from Verification planning to pre-silicon through tape-out. It will also provide a few guidelines that would help to address [...]

2015-06-15T05:44:47+00:0015th June, 2015|Active Event, Blog, Events|

SoC HW/SW Co-Verification Challenges

At DVClub Bangalore on 18th June, Sudhakar Surendran, Technical lead at Texas instruments will presenton “SoC HW/SW Co-Verification Challenges” In recognition of the fact that advent of programmable processors in SoCs have made HW/SW verification an essential part of SoC verification, Sudhakar will address challenges faced in: Verification plan creation Identifying scenarios for HW/SW verification [...]

2015-06-12T05:13:38+00:0012th June, 2015|Active Event, Blog, Events|