Tag Archives: DVClub

DVClub Europe 22 September 2015 – “Power Aware Verification”

TVS is proud to work with Mentor Graphics, ARM, Cadence, Synopsys and Breker to bring the DVClub on Tuesday 22 September. The event will focus on “Power Aware Verification “. You can attend physically (at UWE in Bristol, Cambridge, Grenoble and Sophia) or remotely for free – see here for details and registration.

The agenda for the event as follows:

Event Summary:

  • DVClub Europe, Tuesday 22 September, 2015
  • In-Person: Bristol (New Venue*), Cambridge, Grenoble and Sophia
  • Remote Access (via Internet)
  • Full Program Information

Places are limited and this event is often over-subscribed so we recommend early registration.

Challenges with Power Aware Simulation and Verification Methodologies

Divyeshkumar Dhanjibhai Vora of ARM will discuss “Challenges with Power Aware Simulation and Verification Methodologies” at DVClub Europe Conference on 22 September 2015.

He discusses about proposed enhancements like integrated PA models, liberty based assertions and UPF macro support using successive refinement, to fill the quality holes in the PA simulation flow.

As the modelling complexity is increasing, it requires a thorough check to qualify the above said features in the library models.

Divyeshkumar also discusses a library based validation flow which has been developed in-house at ARM to ensure the qualification of the PA behavior of each library cell against the reference vectors.

  • Power-aware (PA) simulation overview
  • Proposed enhancements in PA simulation
  • Library based validation flow

If you want to find out more about Power Aware Simulation and Verification Methodologies, then join us on the 22nd Sept.

You can attend physically at UWE( in Bristol, Cambridge, Grenoble and Sophia ) or remotely and you can find out more about the conference and how to register here

Low Power Verification with Graph-Based Portable Stimulus

Adnan Hamid, Co-Founder and CTO at Breker Verification Inc., will be at DVClub Europe to discuss “Low Power Verification with Graph-Based Portable Stimulus”.

If you are working on “Low Power Verification“ or wish to get yourself acquainted with the latest in Graph-Based Portable Stimulus, this session is a must attend.

You can attend physically at UWE( in Bristol, Cambridge, Grenoble and Sophia ) or remotely and you can find out more about the conference and how to register here

Successive Refinement: A Methodology for Incremental Specification of Power Intent using UPF

Gabriel Chidolue, Verification Technologist at Mentor Graphics, discusses “A Methodology for Incremental Specification of Power Intent using UPF” at DVClub Europe on 22 September 2015.

Gabriel presentation will cover how to use the UPF Successive Refinement methodology in detail, how it can accelerate design and verification with a re-usable IP to System flow, and simplify the debugging of complex power management architectures.

He will illustrate these advantages by applying the methodology to an ARM® IP-based system design.

If you want to find out more about Power Intent using UPF, then join us on the 22nd Sept.

You can attend physically at UWE( in Bristol, Cambridge, Grenoble and Sophia ) or remotely and you can find out more about the conference and how to register here

DVClub Europe Conference “Power Aware Verification”, 22 September 2015

TVS is proud to work with Mentor Graphics, ARM, Cadence, Synopsys and Breker to bring the DVClub on Tuesday 22 September.The event will focus on “Power Aware Verification “.

You can attend physically (at UWE in Bristol, Cambridge, Grenoble and Sophia) or remotely for free – see here for details and registration.

The agenda for the event as follows:

Event Summary:

  • DVClub Europe, Tuesday 22 September, 2015
  • In-Person: Bristol (New Venue*), Cambridge, Grenoble and Sophia
  • Remote Access (via Internet)
  • Full Program Information

Places are limited and this event is often over-subscribed so we recommend early registration.

SoC Design Verification using 3rd party IPs – Challenges & Guidelines

At DVClub Bangalore on 18 June 2015, Vedantham and Prem C K, Members of Technical Staff, AMD are presenting their experiences in using 3rd party IPs for SoC Design Verification.

This presentation will cover important considerations from Verification planning to pre-silicon through tape-out. It will also provide a few guidelines that would help to address the issues that may potentially compromise the verification quality.

Their presentation will focus on the following Key Points:

  • Interoperability of Vendor IPs.
  • Test planning considerations.
  • Coverage planning considerations.

Vedantham has 14+ years of work experience in multimillion gates ASIC/SOC functional verification. He is familiar with standard ASIC design flow from design concept to tape-outand has participated in many multi-million gate SOC tape-outs .

Prem C K has 15+ years of Verification work experience on IP, Sub-System and System Level and has hands on Experience in Pre and Post silicon Validation.

  • Attending the DVClub conference on June 18is free but places are limited so we recommend early registration.

You can register here

SoC HW/SW Co-Verification Challenges

At DVClub Bangalore on 18th June, Sudhakar Surendran, Technical lead at Texas instruments will presenton “SoC HW/SW Co-Verification Challenges

In recognition of the fact that advent of programmable processors in SoCs have made HW/SW verification an essential part of SoC verification, Sudhakar will address challenges faced in:

  • Verification plan creation
  • Identifying scenarios for HW/SW verification
  • Usecase extraction and mapping to manageable verification items
  • Test case creation
  • Library creation/verification
  • Issues in automation and randomization
  • Testcase execution
  • Run time issues, design/TB optimizations
  • Emulation/Prototyping challenges
  • Debug
  • SW debug challenges
  • Isolating the HW problem
  • Coverage closure

Sudhakar is working as a Technical lead in MCU division at Texas Instruments, currently focusing on Analog integration. He has earlier worked on IP verification, SoCVerification, Emulation, Prototyping, Silicon Validation and Leading teams.Sudhakar has six publications and three patents on verification and micro-architecture.He holds MSc degree from IISc, Bangalore and BE from PSG College of Technology, Coimbatore.

Attending the DVClub conference on June 18 is free but places are limited so we recommend early registration. You can register here