Tag Archives: DVCon Europe

DVCon Europe 2015 to focus on functional safety and innovative verification methods

Building on the success of last years’ inaugural event, DVCon Europe 2015 promises to be bigger and better than ever.For this year’s conference, in addition to the more obvious practices and trends in design and verification, there is a clear focus on functional safety and innovative verification methods, addressing verification at both the IP and system levels. The automotive space is a prominent application domain at DVCon Europe, which is well reflected by introducing a separate track on functional safety, the keynote on automotive issues and trends, and, new this year, a plenary panel session on the automotive semiconductor value chain.

Mike Bartley, CEO of TVS, has been on the DVCon Europe Technical Program Committee for both 2014 and 2015. TVS, a leader in functional safety and innovative verification methods, will therefore have a strong presence at DVCon:

  • Tutorial: Verifying Functional, Safety and Security Requirements (for Standards Compliance)
  • Panel: The Functional Verification Roadmap: Where will we be in Five Years?
  • Poster: A SystemC-based UVM Verification Infrastructure
  • Exhibiting: Stand F2 where you can learn how asureSIGN supports your ISO26262 compliance.

For full details visit the TVS website.

DVCon Europe is a fantastic networking event for design and verification professionals, to meet their peers, as well as EDA, IP and training partners, all under one roof. There is also a rich and diverse exhibition with many well-known and new tool and service providers from around our industry.

This is becoming the premier European event to learn about the latest practices, tools and techniques for IC design and verification. Please look further at the site www.dvcon-europe.org and sign up now!

Where will Functional Verification be in 5 years

Dr.Mike Bartley of TVS, will serve as a panelist with Dr. Raik Brinkmann of OneSpin Solutions, Dr.Holger Busch of Infineon, Colin McKellar from Imagination Technologies and Lauro Rizzatti  to discuss the various areas of advancements required in functional verification for the next five years.

They will attempt to sort out which standards are gaining momentum and recommend a sensible way to develop a functional verification strategy to manage today’s challenges.

If you are at DVCon Europe, then feel free to interact with Mike to discuss the general overview of verification with an emphasis on planning and metrics.

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Demonstrating DO254 & DO178C compliance – see asureSIGN demo at DVCon Europe on November 11-12 at Munich

Markets such as automotive, avionics, nuclear, medical, rail, industrial, etc. require compliance to stringent development standards to ensure the devices are safe. As more devices become connected then security also becomes increasingly important.

Mike Bartley  of TVS, David Kelf from OneSpin Solutions and Dr. Ryan Kastner, co-founder of Tortuga Logic will cover the following topics in detail at DVCon Europe:

  • Defining safety requirements related to ECC (Error Code Correction) mechanisms
  • Identifying security requirements such as privileged accesses to memory.
  • Demonstrating how all requirements can be traced through feature analysis to a verification plan and how that can be traced through to verification execution thus resulting in a proof of implementation for conformance to development standards.

Do say hi to Mike if you spot him. He will be more than happy to discuss DO254 & DO178C compliance with you!

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T&VS to champion Requirements Driven Verification and Test at DVCon Europe

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PRESS RELEASE

Bristol, UK, 29 September 2014 – T&VS, a leader in software test and hardware verification solutions, today announced that is presenting and exhibiting at the inaugural Design & Verification Conference and Exhibition Europe (DVCon Europe) to be held in Munich on 14-15 October 2014 at the Hilton City hotel. The company will be showcasing its driven verification and analogue mixed-signal (AMS) capabilities, together with other product developments.

DVCon Europe is a new conference for the application of software languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. DVCon has run successfully for over twenty years in Silicon Valley, so event organisers are expecting a great deal of interest in the first DVCon Europe.

At DVCon Europe, T&VS will be presenting two papers and one tutorial:

  • T&VS’s tutorial: ‘Requirements Driven Verification and Test (RDVT)’ will be on Tuesday October 14th at 11.30-13.00 and will outline what the development standards mandate and how they can be delivered through requirements-driven verification methodology.
  • T&VS’s first paper: ‘Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVM Verification’ will take place on Wednesday 15 October at 11.30-12 to be presented by T&VS’s Suresh Babu in partnership with Roman Wang of AMD.
  • T&VS’ second paper: ‘Requirements-Driven Verification Methodology (for Standards Compliance)’ will be held later the same day at 16.00-17.00 to be presented by T&VS’s Mike Bartley and Serrie Chapman.

On its DVCon Europe booth, Stand 1, T&VS will be showcasing its latest capabilities and product developments:

  • asureSIGN is a tool for managers, developers and integrators that ensures that product requirements have been successfully tested and implemented.
  • asureCOMPLY makes compliance easier with effective verification in the of safety standards compliance.
  • AMS VIP (Analogue Mixed-Signal Verification IP), offered as part of T&VS’
    asureVIP portfolio, is a suite of tools to provide an efficient, re-usable, development strategy that delivers verification, architecture IP, coverage collection and signoff of AMS designs.

Mike Bartley, CEO of T&VS and DVCon Chair, stated, “Visitors are invited to check out our tutorial and technical talks or come along to our stand for the latest solution demos and announcements; including asureSIGN, our leading-edge leading Requirements Driven Verification tool and our analogue mixed-signal capabilities – or simply stop by for a chat.”

If you’d like to prearrange a meeting at the event please email Mike Bartley of T&VS at: [email protected]

About T&VS
T&VS (Test and Verification Solutions Ltd) provides services and products to organisations developing complex products in the microelectronics and embedded systems industries. Such organisations use T&VS to verify their hardware and software products, employ industry best practice and manage peaks in development and testing programmes. T&VS’ embedded software testing services includes onsite/offshore testing support including assistance with safety certification and security testing. T&VS hardware verification services include onsite/offshore verification support and training in advanced verification methodologies. T&VS also offers Verification IPs and its own Verification (EDA) signoff tool.

T&VS Company Contact
Dr. Mike Bartley – T&VS
+44 7796 307958
[email protected]

Media Contact
Oliver Davies – Publitek Technology PR
+44 1225 470000
[email protected]

A European Twist on DVCon

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DVCon has been running in Silicon Valley since 1988 but is now going on the road, arriving in Munich, Germany on October 14th and 15th 2014, where it will receive a European makeover. In anticipation, I’ve talked to a number of key people involved to find out what the European slant on DVCon will be.

Accellera Systems Initiative is a sponsor of DVCon who provide design and verification standards including IP-XACT, SystemC, SystemVerilog, UPF, UCIS and UVM. This gives DVCon Europe a strong technical theme and thus a great place for engineers to network.

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Visit us at DVCon Europe 2014

dvcon-europe-logoT&VS will be presenting a tutorial and exhibiting at this year’s DVCon in Europe, so if you’re visiting please check out our tutorial and technical talks or come along to our stand for the latest solution demos and announcements; including asureSIGN, our leading-edge leading Requirements Driven Verification tool – or simply stop by for a chat.

The Design and Verification Conference & Exhibition Europe is a new conference for the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits, more details below.

Read the blog article: “A European Twist to DVCon.”

 

What: DVCon Europe 2014
When: October 14-15
Where: Munich, Germany
Event Details: http://dvcon-europe.org
T&VS Stand Location: Stand #1, Strauss Foyer
T&VS Tutorial: Requirements-driven Verification Methodology for Standards Compliance

Requirements-driven verification is based on ensuring that feature-level requirements are adequately verified by tracing such requirements through to verification tasks. It is similar to Coverage-driven Verification from the sense that it is metric-driven but differs significantly because the metrics derive from requirements rather than verification goals

Requirements-driven verification is also required for compliance with the increasing number of standards that control development of hardware for domains such as automotive (ISO26262) and avionics (DO254). The tutorial will cover what the development standards mandate and how it can be delivered through requirements-driven verification methodology and will use an automotive example (lane crossing) to cover the three main issues regarding standards compliance and how they are covered through a requirements-driven verification methodology.

Read the Full Tutorial Details on the DVCon Europe website.

T&VS Talk #1: Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVM Verification

  • Wednesday, Oct 15, 11:30-12:30 [Session T2.4: Advanced Verification]
  • Presented by: Suresh Babu (Test and Verification Solutions) and Roman Wang (AMD)
T&VS Talk #2: Requirements-Driven Verification Methodology (for Standards Compliance)

  • Wednesday, Oct 15, 16:00-17:00 [Session T7.2: Verification Management]
  • Presented by: Serrie Chapman and Mike Bartley – Test and Verification Solutions
T&VS Talk #3: A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog AMS

  • Wednesday, Oct 15, 10:00-11:00 [Session T1.2: Analog / Mixed-Signal Design and Verification]
  • Presented by: Jeganath Gandhi Rajamohan, Mike Bartley – Test and Verification Solutions

About DVCon Europe

The Design and Verification Conference & Exhibition Europe is a new conference for the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, systems designers, software developers and IP integrators the latest methodologies, techniques, applications and demonstrations on the practical use of EDA and IP languages and standards used in electronic design.

For more information visit: http://dvcon-europe.org/conference/dvcon-europe-2014/