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Putting emulation on the map

Emulation is unique in its ability to be deployed in several modes, from traditional in-circuit emulation (ICE), and transaction-based acceleration (TBX). This article from Tech Design Forum outlines the use of emulation for hardware debug, hardware/software co-verification or integration, system-level prototyping, low-power verification,power estimation and performance characterization. Read More

2015-10-05T06:36:23+00:005th October, 2015|Blog, Thought Leadership|

DVCon India panel on “Supporting the Evolving Verification Flow”

Dr.Mike Bartley, CEO & Founder of T&VS was a panelist for the session “Supporting the Evolving Verification” at DVCon India in Bangalore on 10 September 2015 with Lauro Rizzatti, Manish Singh and Sanjay Gupta from Mentor Graphics to develop a strategy for managing an evolving verification flow. Mike has been involved in DVCon for a [...]

2018-02-23T12:46:04+00:0028th September, 2015|Active Event, Blog, Events|

Discuss the latest in verification with T&VS at DVCon India 2015!

T&VS have a strong presence at DVCon India this year. Dr. Mike Bartley, founder and CEO, is serving on the panel for the session ‘Supporting the Evolving Verification flow’ at DVCon India 2015’ with LauroRizzatti and Sanjay Gupta of Mentor Graphics on 10th September. He is also chairing session D1A1.1-DV of the DV track between 13.30 – [...]

2015-11-26T06:19:47+00:009th September, 2015|Active Event, Blog, Events|

T&VS is presenting on M-PHY Analog Modelling and Verification at DVCon India

At DVCon India Mallikarjuna Reddy, Venkatramana Rao and Somanatha Shetty from T&VS are presenting on ‘M-PHY Analog blocks Modelling and Verification using SV/UVM-MS'. In this presentation, T&VS explore how application of advanced AMS modelling techniques help in minimizing the run time significantly for mixed signal designs .T&VS also present benefits of developing SV/UVM-MS environment for [...]

2015-09-07T07:22:34+00:007th September, 2015|Active Event, Blog, Events|

DVCon India Call for Papers

After a very successful first year, DVCon returns to India on Sept 10 - 11.The Design and Verification Conference and Exhibition India is a highly technical conference in India targeting the application of standardised languages, tools and methodologies for the design and verification of electronic systems, embedded systems and integrated circuits. Hosted by Accellera Systems [...]

2015-06-22T06:10:42+00:0022nd June, 2015|Active Event, Blog, Events|

Is SystemC Broken?

It is said that everything in EDA takes 10 years to become adopted. SystemC is more than 15 years old and remains on the horizon. How broken is it? The industry thought it had found the answer with SystemC, but even though that language is now well over ten years old, it has not seen the [...]

2015-08-03T11:22:33+00:002nd June, 2015|Blog, SystemC, Thought Leadership|

Experience the DVContinuum

Experience the DVContinuum : Oliver Bell, Intel Mobile Communications, Germany What’s the DVContinuum? For more than 25 years, DVCon is the premier conference to discuss challenges and achievements for Functional Design and Verification of Electronic Systems and Integrated Circuits. The DVContinuum includes the well-established DVCon United States in March, augmented with DVCon India in September [...]

2015-07-15T15:03:08+00:007th May, 2015|Active Event, Blog, Events, SystemC|

DVCon Call for papers Deadline Extended

DVCon Europe has announced an extension on the Call for Papers to 11th  May 2015. After a very successful launch conference in 2014 the conference returns again to Munich in November 2015. Papers for the conference should be in one of the following 4 topic areas: System-level design IP reuse and design automation Verification & [...]

2018-02-23T12:34:08+00:004th May, 2015|Blog, Thought Leadership|