Tag Archives: DVCon

Putting emulation on the map

Emulation is unique in its ability to be deployed in several modes, from traditional in-circuit emulation (ICE), and transaction-based acceleration (TBX).

This article from Tech Design Forum outlines the use of emulation for hardware debug, hardware/software co-verification or integration, system-level prototyping, low-power verification,power estimation and performance characterization.

Read More

DVCon India panel on “Supporting the Evolving Verification Flow”

Dr.Mike Bartley, CEO & Founder of T&VS was a panelist for the session “Supporting the Evolving Verification” at DVCon India in Bangalore on 10 September 2015 with Lauro Rizzatti, Manish Singh and Sanjay Gupta from Mentor Graphics to develop a strategy for managing an evolving verification flow.

Mike has been involved in DVCon for a number of years for both Europe and India. He also served in this year’s DVCon Technical Program Committee (DV-TPC) to help  shortlist the papers and posters.





TVS Company Contact
Dr. Mike Bartley – TVS
+44 7796 307958
[email protected]

Discuss the latest in verification with T&VS at DVCon India 2015!

T&VS have a strong presence at DVCon India this year. Dr. Mike Bartley, founder and CEO, is serving on the panel for the session ‘Supporting the Evolving Verification flow’ at DVCon India 2015’ with LauroRizzatti and Sanjay Gupta of Mentor Graphics on 10th September. He is also chairing session D1A1.1-DV of the DV track between 13.30 – 15.00 the same day.

On the 11th, Mallikarjuna, Venkat and Somanatha from T&VS are presenting a paper on AMS Verification titled ‘MIPI M-PHY Analog Modelling with Verilog-AMS (Wreal) and Verification using SV/UVM-MS Methodology’.

Do say hi to Mike, Mallikarjuna, Venkat and Somanatha if you spot them. They will be more than happy to discuss verification with you!

T&VS is presenting on M-PHY Analog Modelling and Verification at DVCon India

At DVCon India Mallikarjuna Reddy, Venkatramana Rao and Somanatha Shetty from T&VS are presenting on ‘M-PHY Analog blocks Modelling and Verification using SV/UVM-MS’.

In this presentation, T&VS explore how application of advanced AMS modelling techniques help in minimizing the run time significantly for mixed signal designs .T&VS also present benefits of developing SV/UVM-MS environment for verifying stand-alone M-PHY analog top and end-to-end M-PHY feature verification.

If you are working on M-PHY Verification or wish to get yourself acquainted with the latest in AMS Verification, this session is a must attend. Reserve your slot for the D2A2.3-DVsession at Sitara now!

Dr. Mike Bartley is at DVCon India on 10th September 2015

Dr. Mike Bartley, CEO & Founder of T&VS, is serving on the panel for the session ‘Supporting the Evolving Verification flow’ at DVCon India 2015’ with LauroRizzatti and Sanjay Gupta of Mentor Graphics. He is also chairing session D1A1.1-DV of the DV track between 13.30 – 15.00 on Thursday, September 10th.

Mike has been involved in DVCon for a number of years – initially in the US as both speaker and attendee but more recently on the Technical program Committee (TPC) for both Europe and India.

If you are at DVCon India on the 10th, feel free to interact with Mike to discuss the latest trends in verification.

DVCon Europe making it easier to keep your knowledge up-to-date

After a very successful launch of DVCon Europe in 2014, we can now look forward to a bigger better event in Munich on November 11th and 12th

Sponsored by Accellera Systems Initiative, DVCon is long established in the US but now also runs in Europe and India. It brings chip architects, systems designers, software developers and IP integrators the latest methodologies, techniques, applications and demonstrations on the practical use of EDA and IP languages and standards used in electronic design.

DVCon in Munich adds a European focus reflected in the topics covered: System-level design; Verification & Validation; IP reuse and design automation; Mixed-signal design and verification; Low power techniques; and also Design for functional safety. Attendees can learn how others are dealing with challenges in these areas through approximately 27 papers,  16 posters and 16 tutorials from 40 different companies. Those 40 companies include the major EDA vendors; IP vendors such as ARM and Imagination; semiconductor companies including Infineon, NXP, Intel,  Freescale, Marvell and ST; system companies such as Siemens and Bosch; and major Universities and research organisations.

Of course, with over 350 delegates and 20 booths expected then as well as the formal opportunities for learning there is also the chance to network and see the latest tool innovations.

DVCon is establishing itself as the major European Design and Verification conference. Definitely the place to be – find out more details and how to register here (registration opens September 1st – put it in your diary).

Also, note that DVCon Europe 2015 exactly coincides with two very large trade fairs in Munich so you are advised to book your travel and accommodation early!

Looking forward to meet you at DVCon Europe in Munich!

DVCon India Call for Papers

After a very successful first year, DVCon returns to India on Sept 10 – 11.The Design and Verification Conference and Exhibition India is a highly technical conference in India targeting the application of standardised languages, tools and methodologies for the design and verification of electronic systems, embedded systems and integrated circuits. Hosted by Accellera Systems Initiative, the format of DVCon India is similar to the successful DVCon United States conference held for over 10 years in Silicon Valley.

Mike Bartley, CEO of TVS, is proud to once again serve on the Technical Programme Committee of the Design and Verification Track. You can alsocontribute by delivering a paper or tutorial. The deadline for submission of abstracts is June 30.

Follow this link to understand how to submit your abstract.

Is SystemC Broken?

It is said that everything in EDA takes 10 years to become adopted. SystemC is more than 15 years old and remains on the horizon. How broken is it?

The industry thought it had found the answer with SystemC, but even though that language is now well over ten years old, it has not seen the necessary amounts of investment or adoption and few of its problems have been solved.

Will SystemC even get its act together? That was the focus of a panel at DVCon this year, and while many of the panelists were eager to see its problems resolved, none of them seemed to know the right path forward.

Read more.

Experience the DVContinuum

Experience the DVContinuum :
Oliver Bell, Intel Mobile Communications, Germany

What’s the DVContinuum?

For more than 25 years, DVCon is the premier conference to discuss challenges and achievements for Functional Design and Verification of Electronic Systems and Integrated Circuits. The DVContinuum includes the well-established DVCon United States in March, augmented with DVCon India in September and DVCon Europe in November(Munich, Nov 11- 12, 2015). For each region, DVCon provides a well-chosen mixture of technical paper sessions, tutorials, key notes, posters and exhibits.

Sponsored by Accellera Systems Initiative, DVCon attendees get access to the latest information on various Accellera Standards and its application for system-level design, modelling and verification (including UVM, SystemC, SystemVerilog, IP-XACT and many more). The topics include system-level virtual prototyping, IP reuse, design automation, mixed-signal design, low power design and verification. Facilitating DVCon not only in the US but also in Asia and Europe allow networking and discussions in a much broader audience and expand DVCon’s value to wider community than those only who have the opportunity to travel to the US.

The DVContinuum Anno 2015 – a Historic Perspective 

As DVCon attendee, you will hear a lot about “shift left” and early verification of complex systems. This is not a new concept at all, even it may look like today. A very epic example for a historic shift left had been called out by John F Kennedy in May 1961: “I believe that this nation should commit itself to achieving the goal, before this decade is out, of landing a man on the moon and returning him safely to the earth.” At that time, the required technologies and procedures for a moon landing did not even exist.
For a successful moon mission, not only the actual rocket science engineering but thorough and early verification, continuous learning by the teams and stress testing using system simulation vehicles were key factors.

Looking deeper into the story of the successful Apollo 11 landing on July20, 1969, we get very interesting insights on the importance of the right verification. As the lunar module Eagle made its landing approach to the moon, in short distance to the surface,among other related ones a computer alert 1202 was raised.

Steve Bales, the computer expert in Gene Kranz’s Mission Control team, was able to analyze the alert 1202 quickly as an “Executive overflow” alarm. This simply meant that the computer was in trouble completing its work in the available cycle time. So the right GO for landing decision was made, and no ABORT with maybe fatal consequences. Because exactly this test case was simulated upfront the Apollo 11 mission, Steve Bales was able to correctly analyze this alert so fast. Just two weeks prior to the Apollo 11 launch, simulation supervisor Dick Koos had thrown in a series of program alarms (including the 1202) during the integrated simulations for the stress testing of the flight controllers and the Apollo11 crew’s reaction. During this massive testing, the team had failed with the wrong ABORT decision– two weeks later this simulation experience became real and helped Mission Control for the right decision and supported a successful moon landing.

As you may see from this historical example, the DVContinuum addresses the ever increasing complexity, which was well mastered 50 years ago, and exemplifies the importance for our IC industry. Understanding this DVContinuum is vital to meet the requirements and to address the complexity of the “Systems of Systems” verification.Smarter abstraction techniques, automation, stimuli techniques and above all the creativity of Verification Engineers to create the appropriate simulation models in a very efficient way, will help to continuously shift the limits of verification.
If you are interested to experience the DVContinuum yourself, join us at DVCon Europe and see great examples of yesterday’s, today’s and tomorrow’s systems.Looking forward to meeting you in Munich!

If you like to share your experience with the DVContinuum, submit your paper:  DVCon Europe deadlines are May11th for your draft paper and June 1st for your Tutorial submission.

Find out more about DVCon , DVCon Europe , DVCon India

DVCon Call for papers Deadline Extended

DVCon Europe has announced an extension on the Call for Papers to 11th  May 2015. After a very successful launch conference in 2014 the conference returns again to Munich in November 2015. Papers for the conference should be in one of the following 4 topic areas:

  • System-level design
  • IP reuse and design automation
  • Verification & Validation
  • Mixed-signal design and verification

The Call for Papers requires authors to submit a proposal mainly consisting of a title, an abstract of approximately 100 words, a section that highlights your results including facts and figures, and references if appropriate.

Have you got a story to tell? Then tell it at DVCon Europe.

Read more.