Verification 3.0

I believe we are living in a period of immense change in verification tools, techniques and strategy. This is fostering a number of verification start-ups as well as new tools from the established vendors. Jim Hogan, perhaps the best-known investor in the EDA space, has labelled this revolution “verification 3.0”. Brian Bailey, as always, has [...]

2018-06-06T07:00:01+00:006th June, 2018|Blog, Thought Leadership|

EDA in The Cloud-Part II

This article from Semiengineering captures the conversation between industry experts on the migration of EDA tools into the cloud and describes how should tools be licensed for the cloud, and what is the first application that is likely to see mass adoption. Read More Find out how T&VS Verification services help to meet the challenging [...]

2018-06-05T11:29:54+00:005th June, 2018|Blog, Thought Leadership|

EDA in The Cloud

This article from Semiengineering captures the conversation between industry experts on the migration of EDA tools into the cloud and describes how ready EDA is for the cloud. Read More Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.

2018-05-25T09:58:56+00:0025th May, 2018|Blog, Thought Leadership|

Design Rule Complexity Rising

EDA vendors, chipmakers, IP developers and foundries have been collaborating for at least the past several process nodes, starting at version 0.1 of a process and working all the way up to version 1.0. The growth and complexity of design rules is now a collection of the best ways around problems that all of them [...]

2018-05-03T07:28:25+00:003rd May, 2018|Blog, Thought Leadership|

Raising SoC Development Productivity with Portable Stimulus

The semiconductor industry has achieved significant productivity increases by the development, deployment, and scalability of reusable design IP. The EDA industry has also achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable verification IP. A remaining bottleneck in the SoC development process stems from the inability to reuse verification stimulus [...]

2018-04-27T09:54:47+00:0013th February, 2018|Blog, Thought Leadership|