Tag Archives: EETimes

The Risks & Rewards of Early Tapeout (blog for EETimes)

ee-time-logoIn a recent blog for EETimes, Mike Bartley (founder and CEO of TVS) shared his perspective on the Risks and Rewards of Early Tapeout.  A short abstract of the article is enclosed below. To read the full article visit EETimes.

Early tapeout has one clear advantage. The fastest platform for running tests is the silicon itself. Even the best emulator or FPGA can only operate at a fraction of the speed of the final target, assuming that the SoC can be mapped.

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