Tag Archives: Formal Verification

Doc Formal: When ‘silicon proven’ is not enough

Formal verification is emerging as a viable method for increasing design assurance for VLSI circuits. This article explores how to deploy formal for security in your design verification and summarizes the recommendation for a greater use of formal verification.

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Simulation and Formal – Finding the Right Balance

Simulation dominates hardware functional verification today and likely will continue to dominate for the foreseeable future. Meanwhile formal verification, once thought to be a possible challenger for the title, has instead converged on a more effective role as a complement to simulation.

Formal excels at finding problems in shallow but very broad state graphs and avoids a good deal of the overhead in testbench setup, while simulation has the advantage over formal in deep sequential problems, mixed-level (AMS, SystemC) and asynchronous behaviour modeling. This article highlights why both add to a higher quality result, as long as you get the balance right. Read More


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Formal Property Verification: A tale of two methods

The Formal Property Verification (FPV) methodology often gets used in the last step of verification flow, after much time spent building a complex random constrained UVM environment where some corner cases are still not covered.

Other times, FPV is used when a silicon bug is found that was not raised during the dynamic verification phase. This article examines a case of digital block verification using the formal property verification methodology versus the same block tested in UVM. Read More


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System Level Formal

Two recently announced vulnerabilities in major processor platforms should remind us that bugs don’t organize themselves to appear only in domains we know how to test comprehensively. Both Meltdown and Spectre (the announced problems) are potential hardware system-level issues allowed by interactions between speculative execution and cache behaviour under specialized circumstances.

Finding hardware weaknesses among highly complex interactions is where formal-proving excels, but common belief is that formal analysis on hardware systems of this complexity is beyond the reach of today’s tools, which are typically bounded to block/IP-level proving. This article highlights how to use formal verification for system level verification.

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Doc Formal: the crisis of confidence facing verification III

This article from Tech Design Forum highlights the broad challenges facing semiconductor verification and explain how they have grown to leave us facing a crisis of confidence by summarizing some of the key components of design verification flow such as: why debug represents the biggest contributor to verification cost, while why signoff and review is the most highly valued item in a successful flow.

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Doc Formal: The crisis of confidence facing verification: Part II

This article from Tech Design Forum highlights how to optimize the verification meta model and describes the main components such as requirements & specifications and verification strategy & plan of design verification flow and offer some suggestions as to how they and beyond that the meta model itself should be realized.

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Using sequential equivalence to verify clock-gating strategies

This article from Tech Design Forum explores why formal techniques are powerful, and describes why sequential equivalence checking is a particularly appropriate way to check that a design will work the same way after a clock-gating strategy has been applied.

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The Evolution of Formal Verification – Part Two

As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification. This article from Tech Design Forum explores how formal verification has evolved so that it can now be applied to major project challenges.

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Formal Verification assumes starring role in Automotive

Over the past several years, automotive suppliers made substantial investments to meet ISO 26262 requirements, including the adoption of formal verification. This article from Embedded Computing explores why the formal verification’s ease of use and capacity has made popular in the semiconductor industry and describes why its comprehensive safety critical analysis and diagnostic coverage capabilities make it ideal for automotive and other mission-critical applications.

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