Formal verification (FV) is a promising approach to overcome the coverage limitations of simulation due to its exhaustiveness which enables it to identify intricate design flaws too complex to practically find using simulation. This article outlines what’s the biggest design you can verify with formal. Read More Find out how T&VS Formal Verification techniques helps [...]
Formal verification is emerging as a viable method for increasing design assurance for VLSI circuits. This article explores how to deploy formal for security in your design verification and summarizes the recommendation for a greater use of formal verification. Read More Find out how T&VS Formal Verification techniques helps to improve the quality of Verification.
Simulation dominates hardware functional verification today and likely will continue to dominate for the foreseeable future. Meanwhile formal verification, once thought to be a possible challenger for the title, has instead converged on a more effective role as a complement to simulation. Formal excels at finding problems in shallow but very broad state graphs and [...]
The Formal Property Verification (FPV) methodology often gets used in the last step of verification flow, after much time spent building a complex random constrained UVM environment where some corner cases are still not covered. Other times, FPV is used when a silicon bug is found that was not raised during the dynamic verification phase. [...]
Two recently announced vulnerabilities in major processor platforms should remind us that bugs don’t organize themselves to appear only in domains we know how to test comprehensively. Both Meltdown and Spectre (the announced problems) are potential hardware system-level issues allowed by interactions between speculative execution and cache behaviour under specialized circumstances. Finding hardware weaknesses among [...]
This article from Tech Design Forum highlights the broad challenges facing semiconductor verification and explain how they have grown to leave us facing a crisis of confidence by summarizing some of the key components of design verification flow such as: why debug represents the biggest contributor to verification cost, while why signoff and review is [...]
This article from Tech Design Forum highlights how to optimize the verification meta model and describes the main components such as requirements & specifications and verification strategy & plan of design verification flow and offer some suggestions as to how they and beyond that the meta model itself should be realized. Read More Find out [...]
This article from Tech Design Forum explores why formal techniques are powerful, and describes why sequential equivalence checking is a particularly appropriate way to check that a design will work the same way after a clock-gating strategy has been applied. Read More Find out how T&VS Formal Verification techniques helps to improve the quality of [...]
This article from Tech Design Forum explores some of the key reasons on why semiconductor industry is continuously grappling with inadequate quality despite astronomical growth in constrained random, emulation, and FPGA prototyping. Read More Find out how T&VS Formal Verification techniques helps to improve the quality of Verification.
As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification. This article from Tech Design Forum explores how formal verification has evolved so that it can now be applied to major project challenges. Read More Find out how T&VS Formal Verification [...]