11 Myths About Formal Verification

Formal verification has been available in commercial EDA tools for more than 20 years and in academia much longer.Almost every chip-development team makes use of formal tools, and the market continues to grow. Some myths about formal persist, and they may still be deterring some engineers who could benefit from it. This article explains how [...]

2018-11-15T09:14:37+00:0015th November, 2018|Blog, Thought Leadership|

Doc Formal: Harness the power of invariant-based bug hunting

Formal verification (FV) is a promising approach to overcome the coverage limitations of simulation due to its exhaustiveness which enables it to identify intricate design flaws too complex to practically find using simulation. This article outlines what’s the biggest design you can verify with formal. Read More Find out how T&VS Formal Verification techniques helps [...]

2018-05-30T06:25:13+00:0030th May, 2018|Blog, Thought Leadership|

Doc Formal: When ‘silicon proven’ is not enough

Formal verification is emerging as a viable method for increasing design assurance for VLSI circuits. This article explores how to deploy formal for security in your design verification and summarizes the recommendation for a greater use of formal verification. Read More Find out how T&VS Formal Verification techniques helps to improve the quality of Verification.

2018-02-06T09:55:28+00:006th February, 2018|Blog, Thought Leadership|

Simulation and Formal – Finding the Right Balance

Simulation dominates hardware functional verification today and likely will continue to dominate for the foreseeable future. Meanwhile formal verification, once thought to be a possible challenger for the title, has instead converged on a more effective role as a complement to simulation. Formal excels at finding problems in shallow but very broad state graphs and [...]

2018-01-30T07:32:14+00:0030th January, 2018|Blog, Thought Leadership|

Formal Property Verification: A tale of two methods

The Formal Property Verification (FPV) methodology often gets used in the last step of verification flow, after much time spent building a complex random constrained UVM environment where some corner cases are still not covered. Other times, FPV is used when a silicon bug is found that was not raised during the dynamic verification phase. [...]

2018-01-24T02:28:41+00:0024th January, 2018|Blog, Thought Leadership|

System Level Formal

Two recently announced vulnerabilities in major processor platforms should remind us that bugs don’t organize themselves to appear only in domains we know how to test comprehensively. Both Meltdown and Spectre (the announced problems) are potential hardware system-level issues allowed by interactions between speculative execution and cache behaviour under specialized circumstances. Finding hardware weaknesses among [...]

2018-01-16T09:51:25+00:0016th January, 2018|Blog, Thought Leadership|

Doc Formal: the crisis of confidence facing verification III

This article from Tech Design Forum highlights the broad challenges facing semiconductor verification and explain how they have grown to leave us facing a crisis of confidence by summarizing some of the key components of design verification flow such as: why debug represents the biggest contributor to verification cost, while why signoff and review is [...]

2017-12-12T11:44:31+00:0012th December, 2017|Blog, Thought Leadership|

Doc Formal: The crisis of confidence facing verification: Part II

This article from Tech Design Forum highlights how to optimize the verification meta model and describes the main components such as requirements & specifications and verification strategy & plan of design verification flow and offer some suggestions as to how they and beyond that the meta model itself should be realized. Read More Find out [...]

2017-12-06T08:07:12+00:006th December, 2017|Blog, Thought Leadership|

Using sequential equivalence to verify clock-gating strategies

This article from Tech Design Forum explores why formal techniques are powerful, and describes why sequential equivalence checking is a particularly appropriate way to check that a design will work the same way after a clock-gating strategy has been applied. Read More Find out how T&VS Formal Verification techniques helps to improve the quality of [...]

2017-11-15T06:47:50+00:0015th November, 2017|Blog, Thought Leadership|