Tag Archives: FPGA verification

FPGA Verification Technology Adoption Trends

FPGAs offer real value in verification when they are deployed to help build a significant part of the system or used in multiple instances that allow a design to be re-spun until the functionality is correctly verified.

The unique advantage they bring as a verification tool is that FPGAs are able to run closer to system speed than any other verification technology and can interface to a wide variety of stimulus and test equipment. This article from Mentor Graphics outlines how to adopt the trends of modern FPGA verification technology.

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Trends of FPGA Verification

FPGA Verification complexity is being driven by more than just increased functionality. As devices grow and become more complex resembling complete systems, the task of verifying such a system becomes daunting and the modern FPGA designer faces many different challenges. This article from Mentor Graphics describes how to overcome the challenges of the emerging trends in the architecture of FPGAs.

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FPGA Prototyping as a Verification Methodology

FPGA prototyping is an approach that can greatly assist the development team in producing a quality design in a timeframe that reduces the time to market. This article explores the forces behind the recent increase in FPGA prototyping, reviews the traditional verification techniques, discusses how FPGA prototyping can be part of the verification effort, and gives examples of how verification logic can be incorporated in the FPGA prototype.

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FPGA Verification Techniques For Avionics Applications

As avionics systems grow in complexity, and with the increased use of FPGAs, hardware verification is a major concern within the aerospace sector. This article from Aldec explores how the FPGAs seeking DO-254 compliance face considerable challenges, with a strict requirements-based design and verification process that must be followed to ensure that the product functions as intended.

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FPGA Verification Effectiveness Trends

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. FPGA designs are growing in complexity and the traditional verification methodologies are no longer sufficient. This article from Mentor Graphics focuses on the effectiveness of verification in terms of FPGA project schedule and bug escapes.

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Find out how T&VS delivers flexible and effective FPGA Verification Services.

EZ-VIP Package for Enhanced Testbench Productivity

Mentor Graphics announced the availability of the EZ-VIP productivity package for ASIC and FPGA Verification teams using Questa® Verification IP (QVIP).

This package increases productivity by reducing the time spent, instantiating, configuring and connecting up a QVIP testbench.This means verification teams have more time available to use QVIP to verify that their design is functionally correct.

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Scale & Scalability – The Keys to True FPGA-Based Verification

FPGAs are an extremely flexible platform for the verification of SoC designs, at all levels of the design, and at all stages of the project.

As SoC designs have grown in size and complexity, the need for simulation acceleration and FPGA-based prototypes has kept pace only by employing the very largest and most advanced FPGA technologies.

Alongside this growth, advances in transactors and verification environments, such as UVM, have made it not only possible, but also necessary, to fully integrate simulation and FPGA hardware. This need for scale and scalability has led us from FPGAs being used mainly for prototyping to this new era of FPGA-based verification.

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FPGA Verification done the smart way – the Bluepearl way!

Over the last half-a-decade, FPGAs have been becoming larger and larger in capacity and narrow/deep in technology nodes.  Given the cost advantages of FPGA, various companies that were erstwhile ASIC-only design houses have taken FPGA as the first step to production and/or prototyping. As learnt in the ASIC domain, as designers’ ability to push more logic into a single chip grows, the verification of the functionality, timing and related aspects start exploding.

Just like the way the HDL synthesis requires specific tweaksforASIC vs. FPGA, the verification also requires tweaks and solutions to target FPGA verification. This has been the focus of Blue Pearl Software Inc (BPS)

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