Abstracting Abstracter Abstractions in Functional Verification

This article from Semiengineering outlines why with the upcoming portable stimulus standard we need to consider whether abstraction is really the answer to everything. Read More How Can T&VS Help with Portable Stimulus? T&VS are a leading expert in test and verification and having worked on numerous complex test and stimulus projects and are therefore [...]

2018-04-27T09:17:33+00:00 10th April, 2018|Blog, Thought Leadership|

When Is Verification Done?

Deciding when verification is done is becoming a much more difficult decision, prompting verification teams to increasingly rely on metrics rather than just the tests listed in the verification plan. This article explores why does the complete verification process depends on the increasing number of very complicated factors. Read More Find out how T&VS Verification [...]

2017-08-30T05:57:55+00:00 1st September, 2017|Blog, Thought Leadership|

Parallel Debug: A Path to a Better Big Data Diaspora

The EDA industry is increasingly avaricious for the benefits of big data. While functional verification has been a producer of big data for several years, paradoxically, big data analysis adoption may not have progressed as quickly as it could have due to a shortage of big data consumers. This article describes a methodology parallel debug [...]

2017-08-22T10:08:41+00:00 22nd August, 2017|Blog, Thought Leadership|

Complementing Functional Verification Using Available Timing Information

Functional verification is often focused on verification of the logical functions of the design. In recent years, requirements for better power performance has brought the power implementation aspect of design more into the functional verification side. Similarly, on the timing side the increased complexity of implementation, and clock complexity, as well as greater challenges for [...]

2017-03-09T04:22:25+00:00 9th March, 2017|Blog, Thought Leadership|

Gaps in the Verification flow

This article from Semiengineering captures the conversation from the industry experts, Cadence, Agnisys, OneSpinSolutions and Dr. Mike Bartley, CEO & Founder of Test and Verification Solutions, on how the semiconductor industry is managing to keep up with the demands for functional verification. Read More

2016-10-12T06:36:48+00:00 12th October, 2016|Blog, Thought Leadership|

Safety critical systems and functional verification

This article from Chip Design describes how safety critical verification solution provides functional safety analysis and allows higher systematic verification coverage. Read More Find out how T&VS provides a complete formal verification solution ranging from rigorous verification, and qualification of the verification environment, all the way to the verification of safety mechanisms and diagnostic coverage.

2016-07-07T07:20:30+00:00 7th July, 2016|Blog, Thought Leadership|

Functional Verification Closure- Are we done yet?

Functional verification is the task of verifying that the logic design conforms to specification. It can be and is imprecise—how many tests we need, how much functional coverage is necessary for a high-quality design, how do we know we have a comprehensive verification plan, how many assertions should be implemented, and many more. This article from Cadence [...]

2016-02-29T06:14:09+00:00 29th February, 2016|Blog, Thought Leadership|

Verification Grows Up

Functional verification is used to determine if a design, or unit of a design, conforms to its specification. Making sure a chip will work properly is the fastest-growing aspect of the entire design flow. This article from Semiengineering outlines the conversation of two Verification Consultants, Lauro Rizzatti and Mike Baird on why verification has been [...]

2016-01-07T05:57:07+00:00 7th January, 2016|Blog, Thought Leadership|

Gaps in Performance, Power Coverage

The semiconductor industry always has used metrics to define progress, and in areas such as functional verification. But so far, no effective metrics have been developed for power, performance, or other system-level concerns. This article from SemiEngineering outlines the conversation from Cadence, Mentor graphics on “How power management is well serviced by the tools and [...]

2015-11-27T06:37:00+00:00 27th November, 2015|Blog, Thought Leadership|
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