Deciding when verification is done is becoming a much more difficult decision, prompting verification teams to increasingly rely on metrics rather than just the tests listed in the verification plan. This article explores why does the complete verification process depends on the increasing number of very complicated factors.
Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.
The EDA industry is increasingly avaricious for the benefits of big data. While functional verification has been a producer of big data for several years, paradoxically, big data analysis adoption may not have progressed as quickly as it could have due to a shortage of big data consumers.
This article describes a methodology parallel debug as well as a supporting Jenkins framework, enabled by the availability of massive processor and disc farms which are commonplace among chip design projects.
Find out how T&VS have developed a unique process that enables companies to make continuous improvements to their design and verification environments.
Functional verification is often focused on verification of the logical functions of the design. In recent years, requirements for better power performance has brought the power implementation aspect of design more into the functional verification side. Similarly, on the timing side the increased complexity of implementation, and clock complexity, as well as greater challenges for closing timing requires a closer look at the verification of the functional aspects of the design early on.
This article from Mentor Graphics describes why the relationship between the functional and timing side of equations in clock-domain crossing verification requires a close analysis of timing to gain accuracy and efficiency on the functional side.
Learn how T&VS describes the various areas of advancements required in functional verification for the future years.
This article from Semiengineering captures the conversation from the industry experts, Cadence, Agnisys, OneSpinSolutions and Dr. Mike Bartley, CEO & Founder of Test and Verification Solutions, on how the semiconductor industry is managing to keep up with the demands for functional verification.
This article from Chip Design describes how safety critical verification solution provides functional safety analysis and allows higher systematic verification coverage.
Find out how T&VS provides a complete formal verification solution ranging from rigorous verification, and qualification of the verification environment, all the way to the verification of safety mechanisms and diagnostic coverage.
Functional verification is the task of verifying that the logic design conforms to specification. It can be and is imprecise—how many tests we need, how much functional coverage is necessary for a high-quality design, how do we know we have a comprehensive verification plan, how many assertions should be implemented, and many more. This article from Cadence describes why functional verification can only be addressed by a well-defined and prescribed methodology.
Learn more about T&VS Functional Verification
Functional verification is used to determine if a design, or unit of a design, conforms to its specification. Making sure a chip will work properly is the fastest-growing aspect of the entire design flow. This article from Semiengineering outlines the conversation of two Verification Consultants, Lauro Rizzatti and Mike Baird on why verification has been given high regard within the industry.
Learn more about T&VS Hardware Verification
The semiconductor industry always has used metrics to define progress, and in areas such as functional verification. But so far, no effective metrics have been developed for power, performance, or other system-level concerns.
This article from SemiEngineering outlines the conversation from Cadence, Mentor graphics on “How power management is well serviced by the tools and right coverage metrics”.
Adam Sherer, Product Management Group Director at Cadence, recently spoke on “Unified Safety and Functional Verification” at the DVClub Europe Conference-“Functional Safety in Hardware Verification” which took place on 20 October 2015.
You can view the Slides and Recordings here
Dr.Mike Bartley of TVS, will serve as a panelist with Dr. Raik Brinkmann of OneSpin Solutions, Dr.Holger Busch of Infineon, Colin McKellar from Imagination Technologies and Lauro Rizzatti to discuss the various areas of advancements required in functional verification for the next five years.
They will attempt to sort out which standards are gaining momentum and recommend a sensible way to develop a functional verification strategy to manage today’s challenges.
If you are at DVCon Europe, then feel free to interact with Mike to discuss the general overview of verification with an emphasis on planning and metrics.