T&VS are looking for contractors to perform UVM verification in Germany as soon as possible. Please contact us if you have good UVM experience and you are able to work in Germany immediately.
Please contact Mike Bartley ([email protected]) if you are interested.
Next week over 250 verification engineers will gather to discuss their verification challenges and discuss potential solutions (with another 80 online).
Verification is now the biggest task in any new semiconductor development. Engineers and manager face a range of challenges ranging from integrating data from a range of tools, through measuring test bench quality, how to find bugs earlier and improving vertical reuse, to resourcing projects. We will also look at the different challenges posed in FPGA verification. Plus the 50 challenges posed at previous conferences. You must be facing at least one of those challenges so why not come along and see if you can find a solution?
Registration is easy and free, and includes lunch, refreshments, conference bag and proceedings. We are in Munich, Reading and Sophia, with remote access too of course.
Why not register now or forward this to a colleague?
It is now just 3 weeks until Verification Futures starts a week of Verification Conferences around Europe in Germany, the UK and France. Here are 238 good reasons to attend:
- 21 Verification Challenges from 6 different companies (Broadcom, ST, Samsung, Altera, Ericsson, Infineon) plus a review of all challenges to date
- 9 leading EDA Verification vendors (Synopsys, Mentor, Cadence, Jasper, Doulos, OneSpin, Breker, Aldec and Real Intent)
- 8 user papers
Over 200 registrations to date and still rising.
Registration is free for Reading and Sophia including free lunch, refreshments, conference bag and proceedings. It gives you the chance to catch up with all of the vendors in one place in one day plus other verification engineers.
I am pleased to announce the availability of some of the recordings from the TVS Verification Futures 2012 conferences held across Europe during November. The recordings contain the slides and the speaker explanation – so give a lot of value than the slides alone
Please note that unfortunately some of the recordings are better quality than others.
I hope you enjoy the recordings and find them useful. We will soon be announcing our Worldwide plans for Verification futures 2013
An opportunity to meet and discuss your verification challenges with both verification thought leaders and colleagues from other companies. Speakers from a number of semiconductor companies will lay out their verification challenges.
Geoff Barrett of Broadcom, UK talks about scalability of simulations and hardware/software coverification. The challenges from Christophe Chevallaz of ST, France include system level stimulation and the management of verification data. Martin Ruhwandl of Lantiq, Munich identifies debug. Most speakers identify access to skilled verification engineers as a key challenge. All in all speakers from 12 companies will identify their top three challenges.
See /verification-futures/ for details.
The day is spent identifying solutions to these challenges. Top international speakers including Harry Foster, Mentor and Janick Bergeron, Synopsys will give their view of how verification tools and techniques will evolve to meet the challenges. Every major EDA company will explain how their tools can solve the 36 challenges identified!
There are also over 12 user papers across the three conferences in Windsor, Grenoble and Munich – real verification engineers talking about how they solved their own challenges.
The good news is that the verification conference is free to attend. Why not register for your nearest event and take this unique opportunity to spend a day trying to solve your verification challenges.
Verification Futures 2012 is a ‘one-stop-shop’ offering the perfect opportunity to network, as well as the chance to discuss your verification challenges with others facing similar problems.
The conference series, FREE to attend and taking place over three days in three different European locations, provides a unique opportunity to meet all of the EDA vendors in one place on one day and hear about their verification solutions. It also provides an opportunity to network with verification engineers from a wide range of companies, discuss your verification challenges and share your solutions. A unique day which should not be missed.
19th November (Windsor, UK)
21st November (Grenoble, France)
22nd November (Munich, Germany)
Book now! We sold out last year and had to disappoint those who didn’t register early, book now to avoid disappointment!!
Don’t forget that the conferences are also available by remote access for those who can’t attend!
EETimes Europe asked Mike Bartley of leading verification house TVS to look at how European companies see the challenges and possible solutions. Read the article here.
The major silicon companies inEuropesee the rise in design complexity as a major verification challenge but see different methods of solving this.
These topics are covered at the Verification Futures conference held in UK, France and Germany during the week of November 19th 2012
Bristol, England – 1st October 2011: T&VS today announces the opening of offices in Hanau, Germany providing hardware verification and embedded software testing services to the micro electronics industry in central Europe.
Dr. Mike Bartley, T&VS CEO comments, “we already supply services into mainland Europe but this new office will allow us to expand our offering. Organisations are increasingly asking for timely access to skilled engineering personnel and we need a local presence to rapidly process visa applications and put a team in place with the right skills profile anywhere in the Schengen region.”
T&VS is expanding rapidly from its UK base. It opened offices in Chennai, India in August this year to serve client projects across Europe and India. Mike Bartley added, “T&VS clients across Europe are choosing our off-shore capability in India and our German office is a necessary step in expanding our services in Europe and satisfying customer engagements.”
T&VS provides services and products to organisations developing complex products in the micro-electronics and embedded systems industries. Such organisations use T&VS to verify their hardware and software products, employ industry best practice and manage peaks in development and testing programmes. T&VS has its headquarters in Bristol, England with offices in Europe and India.
Note to Editors:
Further information on T&VS products and services is available at www.testandverification.com
Dr. Mike Bartley
+44 (0) 7796 307958