Hardware Emulation in Mid-Life — Moving to Center Stage

In the early days, hardware emulation was used for only the most sophisticated, challenging designs at the time. Verification Consultant, Lauro Rizzatti, describes how hardware emulation moved into the new millennium with a new outlook on SoC chip design verification. Read More Find out how T&VS Hardware Emulation services allow verifying the robustness of a [...]

2018-02-27T05:19:09+00:00 27th February, 2018|Blog, Thought Leadership|

Design-For-Testability (DFT) Verified with Hardware Emulation

A DFT App enables execution of complete pattern sets for DFT verification in a reasonable time to shorten the pattern development cycle. Verification Consultant, Lauro Rizzatti, explores how an emulation session provides enough verification power to pull the DFT schedule within the time the project management has scheduled, thus accelerating the time to market, increasing [...]

2018-02-06T10:11:34+00:00 6th February, 2018|Blog, Thought Leadership|

Design Verification Strategies and Hardware Emulation

Verification Consultant, Lauro Rizzatti, describes the solutions that are being asked by chip designers and verification engineers on why is emulation suddenly the foundation of design verification flows and what kind of announcements about hardware emulation can expect to see in 2017 that support new markets, such as IoT, automotive, safety, and security. Read More [...]

2017-01-17T12:04:06+00:00 17th January, 2017|Blog, Thought Leadership|

Moving DFT into chip design with hardware emulation

Design for Testability (DFT) consists of IC design techniques that add testability features to a hardware product design. The added features make it easier to develop and apply manufacturing tests to the designed hardware. Verification Consultant, Lauro Rizzatti, describes how hardware emulation provides enough verification power to move DFT into the chip design thus accelerating [...]

2016-11-22T06:28:00+00:00 22nd November, 2016|Blog, Thought Leadership|

The Emulator thrives as verification models mushroom

Greater time-to-market pressures, along with escalating hardware/software integration and quality concerns, are making the verification process a strategically important step in chip design. Coming to the rescue is a new generation of cost-effective hardware emulators. This article from Tech Design Forum explores why hardware emulation has moved into the verification mainstream and why it is [...]

2016-10-25T06:10:11+00:00 25th October, 2016|Blog, Thought Leadership|
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