Not All Emulators Are Created Equal

For a verification technology that wasn’t well known outside of the largest semiconductor designs until a decade ago, hardware-emulation adoption has grown considerably over the past few years. This article describes why this sudden increase in hardware-emulation deployment within the design-verification flow and outlines why speed, throughput, and latency are the key parameters in determining [...]

2018-06-28T09:28:36+00:00 28th June, 2018|Blog, Thought Leadership|

Not All Emulators Are Created Equal

For a verification technology that wasn’t well known outside of the largest semiconductor designs until a decade ago, hardware-emulation adoption has grown considerably over the past few years. This article describes why this sudden increase in hardware-emulation deployment within the design-verification flow and explains why speed, throughput, and latency are the key parameters in determining [...]

2018-06-22T06:18:33+00:00 22nd June, 2018|Blog, Thought Leadership|

What Does the Future Hold in Hardware Emulation

Decades after its introduction, hardware emulation now is the preferred choice for design debugging. It satisfies all the verification objectives of a SoC design regardless of its type and application, from hardware verification and hardware/software integration to embedded software and system validation, including post-silicon validation. Verification Consultant, Lauro Rizzatti, summarizes in this article on what [...]

2018-04-26T06:00:32+00:00 26th April, 2018|Blog, Thought Leadership|

Hardware Emulation in Mid-Life — Moving to Center Stage

In the early days, hardware emulation was used for only the most sophisticated, challenging designs at the time. Verification Consultant, Lauro Rizzatti, describes how hardware emulation moved into the new millennium with a new outlook on SoC chip design verification. Read More Find out how T&VS Hardware Emulation services allow verifying the robustness of a [...]

2018-02-27T05:19:09+00:00 27th February, 2018|Blog, Thought Leadership|

Design-For-Testability (DFT) Verified with Hardware Emulation

A DFT App enables execution of complete pattern sets for DFT verification in a reasonable time to shorten the pattern development cycle. Verification Consultant, Lauro Rizzatti, explores how an emulation session provides enough verification power to pull the DFT schedule within the time the project management has scheduled, thus accelerating the time to market, increasing [...]

2018-02-06T10:11:34+00:00 6th February, 2018|Blog, Thought Leadership|

Design Verification Strategies and Hardware Emulation

Verification Consultant, Lauro Rizzatti, describes the solutions that are being asked by chip designers and verification engineers on why is emulation suddenly the foundation of design verification flows and what kind of announcements about hardware emulation can expect to see in 2017 that support new markets, such as IoT, automotive, safety, and security. Read More [...]

2017-01-17T12:04:06+00:00 17th January, 2017|Blog, Thought Leadership|

Moving DFT into chip design with hardware emulation

Design for Testability (DFT) consists of IC design techniques that add testability features to a hardware product design. The added features make it easier to develop and apply manufacturing tests to the designed hardware. Verification Consultant, Lauro Rizzatti, describes how hardware emulation provides enough verification power to move DFT into the chip design thus accelerating [...]

2016-11-22T06:28:00+00:00 22nd November, 2016|Blog, Thought Leadership|

The Emulator thrives as verification models mushroom

Greater time-to-market pressures, along with escalating hardware/software integration and quality concerns, are making the verification process a strategically important step in chip design. Coming to the rescue is a new generation of cost-effective hardware emulators. This article from Tech Design Forum explores why hardware emulation has moved into the verification mainstream and why it is [...]

2016-10-25T06:10:11+00:00 25th October, 2016|Blog, Thought Leadership|
T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.