Total Value of a Portable Stimulus Standard

The creation of the portable stimulus standard has raised several issues about the trade-offs between using an industry standard language and a domain-specific language. This article from Eda Café describes how the inclusion of C++ option provide you with a more powerful solution that fits your needs both today and in the future and that [...]

2018-10-12T05:36:09+00:0012th October, 2018|Blog, Thought Leadership|

Carving Up Verification

This article from Semiengineering explores how the verification is evolving in semiconductor industry and describes how to use the four main engines of verification such as, formal, simulation, emulation and prototyping. Read More Find out how T&VS have developed a unique process that enables companies to make continuous improvements to their design and verification environments.

2018-10-12T05:26:43+00:0012th October, 2018|Blog, Thought Leadership|

When Is Verification Done?

Deciding when verification is done is becoming a much more difficult decision, prompting verification teams to increasingly rely on metrics rather than just the tests listed in the verification plan. This article explores why does the complete verification process depends on the increasing number of very complicated factors. Read More Find out how T&VS Verification [...]

2018-10-12T05:21:06+00:0012th October, 2018|Blog, Thought Leadership|

Breaking Points of Verification

Verification efficiency and speed can vary significantly from one design to the next, and that variability is rising alongside growing design complexity. Depending on design complexity, memory allocation or a host of other issues, several approaches simply can run out of steam. This article focuses on the breaking points of verification and explains why it is [...]

2018-10-12T05:18:46+00:0012th October, 2018|Blog, Thought Leadership|

Moving DFT into chip design with hardware emulation

Design for Testability (DFT) consists of IC design techniques that add testability features to a hardware product design. The added features make it easier to develop and apply manufacturing tests to the designed hardware. Verification Consultant, Lauro Rizzatti, describes how hardware emulation provides enough verification power to move DFT into the chip design thus accelerating [...]

2018-10-12T05:00:44+00:0012th October, 2018|Blog, Thought Leadership|

Using Hardware Secure modules to protect SoCs

Building secure SoCs takes a methodical approach, careful study of possible attacks, and embedded hardware that can provide a Root of Trust. Protecting security in an SoC means protecting the device in all states. This article from Tech Design Forum focuses on how to protect SoCs using hardware security modules. Read More Find out how [...]

2018-02-09T05:45:39+00:009th February, 2018|Blog, Thought Leadership|

Understanding the inner workings of UVM – Part 2

This article highlights the UVM communication protocols set between Sequence, Sequencer and Driver, and describes how the class sequencer interacts with class uvm_sequence to generate stimulus out of sequence_item. Read More Join T&VS UVM training and learn how to improve the verification accuracy and quality for today’s SoC.

2018-02-08T06:39:30+00:008th February, 2018|Blog, Thought Leadership|

Verification of Functional Safety: Part II

Functional safety is becoming a key part of chip design, and an increasingly problematic one for many engineering teams. Functional safety for electrical and electronic systems is nothing new. It has been an essential element in every industry for many years. But the growing importance of functional safety within the automobile industry presents a number [...]

2018-02-07T05:55:09+00:007th February, 2018|Blog, Thought Leadership|