The creation of the portable stimulus standard has raised several issues about the trade-offs between using an industry standard language and a domain-specific language. This article from Eda Café describes how the inclusion of C++ option provide you with a more powerful solution that fits your needs both today and in the future and that [...]
The objective of Portable Stimulus is to be able to write your verification intent once and can use it at all stages of silicon realization. This article from EDA Café summarizes the reasons that states why portable stimulus is the first true verification model. A single Portable Stimulus model can be used as an input [...]
This article from Semiengineering explores how the verification is evolving in semiconductor industry and describes how to use the four main engines of verification such as, formal, simulation, emulation and prototyping. Read More Find out how T&VS have developed a unique process that enables companies to make continuous improvements to their design and verification environments.
Deciding when verification is done is becoming a much more difficult decision, prompting verification teams to increasingly rely on metrics rather than just the tests listed in the verification plan. This article explores why does the complete verification process depends on the increasing number of very complicated factors. Read More Find out how T&VS Verification [...]
Verification efficiency and speed can vary significantly from one design to the next, and that variability is rising alongside growing design complexity. Depending on design complexity, memory allocation or a host of other issues, several approaches simply can run out of steam. This article focuses on the breaking points of verification and explains why it is [...]
Design for Testability (DFT) consists of IC design techniques that add testability features to a hardware product design. The added features make it easier to develop and apply manufacturing tests to the designed hardware. Verification Consultant, Lauro Rizzatti, describes how hardware emulation provides enough verification power to move DFT into the chip design thus accelerating [...]
The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, and there are more DFT integration steps than ever before. The traditional approaches to DFT work on huge [...]
Building secure SoCs takes a methodical approach, careful study of possible attacks, and embedded hardware that can provide a Root of Trust. Protecting security in an SoC means protecting the device in all states. This article from Tech Design Forum focuses on how to protect SoCs using hardware security modules. Read More Find out how [...]
This article highlights the UVM communication protocols set between Sequence, Sequencer and Driver, and describes how the class sequencer interacts with class uvm_sequence to generate stimulus out of sequence_item. Read More Join T&VS UVM training and learn how to improve the verification accuracy and quality for today’s SoC.
Functional safety is becoming a key part of chip design, and an increasingly problematic one for many engineering teams. Functional safety for electrical and electronic systems is nothing new. It has been an essential element in every industry for many years. But the growing importance of functional safety within the automobile industry presents a number [...]