Building secure SoCs takes a methodical approach, careful study of possible attacks, and embedded hardware that can provide a Root of Trust. Protecting security in an SoC means protecting the device in all states. This article from Tech Design Forum focuses on how to protect SoCs using hardware security modules. Read More Find out how [...]
This article highlights the UVM communication protocols set between Sequence, Sequencer and Driver, and describes how the class sequencer interacts with class uvm_sequence to generate stimulus out of sequence_item. Read More Join T&VS UVM training and learn how to improve the verification accuracy and quality for today’s SoC.
Functional safety is becoming a key part of chip design, and an increasingly problematic one for many engineering teams. Functional safety for electrical and electronic systems is nothing new. It has been an essential element in every industry for many years. But the growing importance of functional safety within the automobile industry presents a number [...]
Formal verification is emerging as a viable method for increasing design assurance for VLSI circuits. This article explores how to deploy formal for security in your design verification and summarizes the recommendation for a greater use of formal verification. Read More Find out how T&VS Formal Verification techniques helps to improve the quality of Verification.
The recent explosion of FPGA-based compute acceleration has created an enormous new market opportunity for programmable logic. At the same time, however, eFPGAs represent a serious challenge to FPGAs in capturing the long, big-money tail of the compute acceleration wave. eFPGAs are IP blocks that can be used by custom chip designers to add FPGA [...]
The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, and there are more DFT integration steps than ever before. The traditional approaches to DFT work on huge [...]
Functional safety is becoming a key part of chip design, and an increasingly problematic one for many engineering teams. Verification flow of Functional safety for automotive SoCs must ensure zero design bugs, using coverage-driven functional verification, and zero safety risks, using a functional safety verification strategy that complies with the ISO 26262 automotive safety standard. [...]
An FPGA is an integrated circuit or device that is programmed to perform specific functions after it has been built. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an ASIC. This article provides you the knowledge needed to build a good FPGA foundation. Read More Check out T&VS services [...]
Simulation dominates hardware functional verification today and likely will continue to dominate for the foreseeable future. Meanwhile formal verification, once thought to be a possible challenger for the title, has instead converged on a more effective role as a complement to simulation. Formal excels at finding problems in shallow but very broad state graphs and [...]
VIPs play a very important role in the verification flow of modern SoCs. They can check the correctness of communication over system buses and provide master, slave, decoder, or arbiter components if these are missing in the verification set-up. This article describes verification of RISC-V processors, focusing on the combination of automatically generated UVM verification [...]