Tag Archives: Hardware Verification

Using Hardware Secure modules to protect SoCs

Building secure SoCs takes a methodical approach, careful study of possible attacks, and embedded hardware that can provide a Root of Trust. Protecting security in an SoC means protecting the device in all states. This article from Tech Design Forum focuses on how to protect SoCs using hardware security modules.

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Verification of Functional Safety: Part II

Functional safety is becoming a key part of chip design, and an increasingly problematic one for many engineering teams. Functional safety for electrical and electronic systems is nothing new. It has been an essential element in every industry for many years.

But the growing importance of functional safety within the automobile industry presents a number of new twists. This article from Semiengineering how do you trade off cost and safety within an automobile and outlines how to overcome the challenges the chip industry is facing.

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Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.

Doc Formal: When ‘silicon proven’ is not enough

Formal verification is emerging as a viable method for increasing design assurance for VLSI circuits. This article explores how to deploy formal for security in your design verification and summarizes the recommendation for a greater use of formal verification.

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Find out how T&VS Formal Verification techniques helps to improve the quality of Verification.

Moving from FPGA’s to Embedded FPGA Fabric – How it’s Done

The recent explosion of FPGA-based compute acceleration has created an enormous new market opportunity for programmable logic. At the same time, however, eFPGAs represent a serious challenge to FPGAs in capturing the long, big-money tail of the compute acceleration wave. eFPGAs are IP blocks that can be used by custom chip designers to add FPGA fabric to any custom IC design. This article from Semiwiki summarizes how to move from FPGA’s to embedded FPGA fabric.

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Check out T&VS services that help you know why FPGA technology is making new inroads as demands increase for better integration between hardware and software.

Smarter DFT Infrastructure and Automation Emerge as Keys to Managing DFT Design Scaling

The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, and there are more DFT integration steps than ever before. The traditional approaches to DFT work on huge designs pose problems of repeatability and reliability.

With more DFT steps, the overall rate of success declines unless the rate of success at each step is extremely high. This article from Semiengineering explores how do you ensure an extremely high rate of success at each step in the DFT flow by adopting a smarter technology.

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Verification of Functional Safety

Functional safety is becoming a key part of chip design, and an increasingly problematic one for many engineering teams. Verification flow of Functional safety for automotive SoCs must ensure zero design bugs, using coverage-driven functional verification, and zero safety risks, using a functional safety verification strategy that complies with the ISO 26262 automotive safety standard. This article highlights how do you trade off cost and safety within an automobile and describes some of the challenges the chip industry is facing.

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Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.

Guide to Understanding FPGA Development

An FPGA is an integrated circuit or device that is programmed to perform specific functions after it has been built. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an ASIC. This article provides you the knowledge needed to build a good FPGA foundation.

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Check out T&VS services that help you know why FPGA technology is making new inroads as demands increase for better integration between hardware and software.

Simulation and Formal – Finding the Right Balance

Simulation dominates hardware functional verification today and likely will continue to dominate for the foreseeable future. Meanwhile formal verification, once thought to be a possible challenger for the title, has instead converged on a more effective role as a complement to simulation.

Formal excels at finding problems in shallow but very broad state graphs and avoids a good deal of the overhead in testbench setup, while simulation has the advantage over formal in deep sequential problems, mixed-level (AMS, SystemC) and asynchronous behaviour modeling. This article highlights why both add to a higher quality result, as long as you get the balance right. Read More


Find out how T&VS verification services help you to drive tight links between formal and simulation & ensure highest productivity & product quality.

Tutorial for Connecting Questa® VIP into the Processor Verification Flow

VIPs play a very important role in the verification flow of modern SoCs. They can check the correctness of communication over system buses and provide master, slave, decoder, or arbiter components if these are missing in the verification set-up.

This article describes verification of RISC-V processors, focusing on the combination of automatically generated UVM verification environments by QVIP Configurator and Questa® VIP (QVIP) components and summarizes the step-by-step instructions that demonstrate how to add QVIP components into processor verification environments.

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Find out how T&VS VIPs help verification engineers access to the industry’s latest protocols, interfaces and memories required to verify their SoC designs.