UVM 1.2 to IEEE for Standardization

This article from Accellera outlines how UVM 1.2 builds on the IEEE 1800™ SystemVerilog standard by specifying an application programming interface and explores how Design and verification teams can then use the library to develop modular, scalable and reusable components for functional verification environments. Read More

2015-10-01T06:01:24+00:001st October, 2015|Blog, Thought Leadership|