A Four-Stage Flow for Power Management Verification

Power management verification is critical. organizations start this type of verification at a very early stage in the design flow and add details and granularities as the design progresses. This article describes a four-stage power management verification flow that allows customers to break down a complex problem into smaller, targeted verification projects and establish a [...]

2017-05-10T06:17:55+00:0010th May, 2017|Blog, Thought Leadership|

Verification Strategy for Robust Low power Architecture

To enable the adoption of advanced low-power techniques by mainstream users, there is a need for a design flow that holistically addresses the architecture, design, verification, and implementation of low-power designs.Due to the nature of low power design architectures and behavior, low power verification complexity is exponentially more challenging.  This article from Design Reuse describes [...]

2017-01-06T05:36:31+00:006th January, 2017|Blog, Thought Leadership|

Robust Low power Architecture verification Strategy

Adoption of advanced low power design techniques is growing rapidly to support ever-more sophisticated system level power management schemes. Due to the nature of low power design architectures and behavior, low power verification complexity is exponentially more challenging.  This article from Design Reuse describes how to achieve robust verification coverage of low power architecture. Read [...]

2016-08-03T05:38:12+00:003rd August, 2016|Blog, Thought Leadership|

Is Low Power Coverage Achievable

With increasing design complexities in power architecture and complex power domain partitioning, it is becoming imperative to drive functional and physical verification of these complex power logic hand in hand.Design and verification teams are struggling to keep up with two vectors – the ever increasing number of IP blocks and subsystems in modern SoCs & [...]

2016-05-31T08:03:27+00:0031st May, 2016|Blog, Thought Leadership|

Preparing for low-power Verification success: Setting objectives and measuring outcomes

Functionally verifying complex SoCs is an enormous challenge, and the challenge grows when multiple power domains are powered up and down for power management needs. This article from Synopsys outlines how low-power design strategies affect the verification process and describes the measures to overcome these challenges. Read More

2015-10-19T10:59:38+00:0019th October, 2015|Blog, Thought Leadership|

Low Power Verification with Graph-Based Portable Stimulus

Adnan Hamid, Co-Founder and CTO at Breker Verification Inc., will be at DVClub Europe to discuss “Low Power Verification with Graph-Based Portable Stimulus”. If you are working on “Low Power Verification“ or wish to get yourself acquainted with the latest in Graph-Based Portable Stimulus, this session is a must attend. You can attend physically at [...]

2015-09-21T04:37:55+00:0021st September, 2015|Active Event, Blog, Events|