Tag Archives: Low Power Verification

A Four-Stage Flow for Power Management Verification

Power management verification is critical. organizations start this type of verification at a very early stage in the design flow and add details and granularities as the design progresses. This article describes a four-stage power management verification flow that allows customers to break down a complex problem into smaller, targeted verification projects and establish a feedback loop to and from the backend teams.

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Find how T&VS Verification Services ensures greater efficiency, improve debug, faster time-to-market, and gives design teams the ability to de-risk the challenges of complex chip designs.

Verification Strategy for Robust Low power Architecture

To enable the adoption of advanced low-power techniques by mainstream users, there is a need for a design flow that holistically addresses the architecture, design, verification, and implementation of low-power designs.Due to the nature of low power design architectures and behavior, low power verification complexity is exponentially more challenging.  This article from Design Reuse describes how to achieve robust verification coverage for low power architecture.

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Find out how T&VS Verification services help to meet the challenging requirements with respect to performance, flexibility and verify the today’s complex designs effectively.

Robust Low power Architecture verification Strategy

Adoption of advanced low power design techniques is growing rapidly to support ever-more sophisticated system level power management schemes. Due to the nature of low power design architectures and behavior, low power verification complexity is exponentially more challenging.  This article from Design Reuse describes how to achieve robust verification coverage of low power architecture.

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Find out how T&VS Verification Services enable to support for advanced power management required in many of today’s electronic products.

Is Low Power Coverage Achievable

With increasing design complexities in power architecture and complex power domain partitioning, it is becoming imperative to drive functional and physical verification of these complex power logic hand in hand.Design and verification teams are struggling to keep up with two vectors – the ever increasing number of IP blocks and subsystems in modern SoCs & the growing use of software for power management. This article from Semiengineering describes how to handle and achieve low power coverage. Read More


Find out how T&VS low-power verification flow provides a seamless solution to verification challenges and allows for quick debugging of issues related to errors in the low-power design intent.

Preparing for low-power Verification success: Setting objectives and measuring outcomes

Functionally verifying complex SoCs is an enormous challenge, and the challenge grows when multiple power domains are powered up and down for power management needs.

This article from Synopsys outlines how low-power design strategies affect the verification process and describes the measures to overcome these challenges.

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Low Power Verification with Graph-Based Portable Stimulus

Adnan Hamid, Co-Founder and CTO at Breker Verification Inc., will be at DVClub Europe to discuss “Low Power Verification with Graph-Based Portable Stimulus”.

If you are working on “Low Power Verification“ or wish to get yourself acquainted with the latest in Graph-Based Portable Stimulus, this session is a must attend.

You can attend physically at UWE( in Bristol, Cambridge, Grenoble and Sophia ) or remotely and you can find out more about the conference and how to register here