Mixed-Signal/Low-Power Design

Adding ultra-low-power requirements to a device design is complicating the traditional process of mixed-signal IC design. This article from Semiengineering captures the conversation between Cadence, Mentor Graphics and Synopsys on the challenges of designing the mixed-signal/low-power IC. Read More Find out how T&VS services enable verification engineers to address the challenges of mixed-signal/low-power designs.

2016-08-16T06:14:42+00:00 16th August, 2016|Blog, Thought Leadership|

Energy Efficient Computing SIG – Thursday 18th July

Power consumption is a critical element of today’s computing devices: Even the smartest smart phone or tablet stops working when the battery runs out of power! The predicted limit of the fastest supercomputer is based on the total amount of power consumed rather than compute performance. Most of the predicted 50Billion devices in the Internet [...]

2013-07-15T10:36:51+00:00 15th July, 2013|Events, Latest Press|

John Biggs gives invaluable insight into UPF

At DVClub Europe on July 1st, John Biggs (Chair of the IEEE1801 UPF Working Group) gave an invaluable insight to UPF both current and future.  He first reviewed the main UPF components such as Power Domains, Power Supply Network, Power State Tables, Isolation Strategies, Retention Strategies and Level Shifter Strategies.  John explained all of these [...]

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