Tag Archives: Low Power

Mixed-Signal/Low-Power Design

Adding ultra-low-power requirements to a device design is complicating the traditional process of mixed-signal IC design. This article from Semiengineering captures the conversation between Cadence, Mentor Graphics and Synopsys on the challenges of designing the mixed-signal/low-power IC.

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Find out how T&VS services enable verification engineers to address the challenges of mixed-signal/low-power designs.

Energy Efficient Computing SIG – Thursday 18th July

Power consumption is a critical element of today’s computing devices:

  • Even the smartest smart phone or tablet stops working when the battery runs out of power!
  • The predicted limit of the fastest supercomputer is based on the total amount of power consumed rather than compute performance.
  • Most of the predicted 50Billion devices in the Internet of Things will not be connected to mains – so cannot send data if they run out of power.

The use of digital devices and systems – big or small, complex or simple – are already essential for the intelligence and automation that supports our daily lives…  and they all consume power.  In portable devices there is a constant balancing act between graphics, processing and battery life. The large computer systems that are required for data modeling and processing in today’s “Big Data” society are also a significant proportion of the electricity consumption of developed economies.

The power consumption of a device can set an upper bound on performance available – hence the need for more power efficient compute platforms.

The Energy Efficient Computing SIG (EEC SIG) was funded by the Technology Strategy Board to provide a focus for innovations in this area of technology.  It brings together the communities of ICT KTB and ESP KTN.  One particular perceived challenge was that reductions in power consumption in hardware alone were no longer sufficient to achieve the required performance.  It was essential to gain a better understanding of the problem and then address the solutions as a systems problem – requiring the combined skills of software, hardware and systems design.

This meeting will present some of the work undertaken in the first year of operation of the SIG and a wide range of presentations that cover current and future work being undertaken in industry and research organisations.  It will also cover future support and funding schemes from both the Technology Strategy Board and the EU.

Anyone working with compute platforms will find something of interest.  There will be an opportunity to network with other experts from the sector to share knowledge and seek collaborations.  Register now for this free event at the Ambassadors Bloomsbury Hotel.  For more information click here.

John Biggs gives invaluable insight into UPF

At DVClub Europe on July 1st, John Biggs (Chair of the IEEE1801 UPF Working Group) gave an invaluable insight to UPF both current and future.  He first reviewed the main UPF components such as Power Domains, Power Supply Network, Power State Tables, Isolation Strategies, Retention Strategies and Level Shifter Strategies.  John explained all of these with well-chosen examples.

Given John’s position at ARM, he took time to explain the UPF capability for “Successive Refinement of Design Intent” whereby an IP supplier can supply a “Constraint UPF” along with the RTL. The IP user then adds then adds a “Configuration UPF” to create a golden source for the implementation team which adds an “Implementation UPF” for synthesis etc.

John also gave an overview of the May 2013 release of the standard (UPF-2.1) highlighting the additions made.  John’s slides and a video of his presentation can be found on our website.

The rest of the DVClub was dedicated to verification of UPF designs and can also be found on our website.